Complete AXI wrapper generator (#1934)

* WIP axi-gen main component

Done with input/output, cells, wires, and groups (there are none)
TODO: Control sequence

* Add clearer exceptions in invokes

* get invoke of channels working

* Add `*=` for par block control composition

* Add small runt test for `+=` and `*=`

* add some documentation about *=

* better exceptions py builder

* AXI generator that creates a valid calyx program

TBD If the spec is implemented properly (probably not)

TODO:
1. Get AXI working with cocotb tests
2. Hook up runt tests
3. Refactor/minimize generator code
4... Fud2 integration?

* Revert "Merge branch 'builder-qol' into py-axi-gen-main"

This reverts commit a9628ce, reversing
changes made to 7a28be6.

* Add invocation and instantiaion of main_compute

* Attempt at generalizing attributes

* Add component attribute support to builder

* update invoke.py in test/

* typo fix in docs

* Add toplevel attribute to `wrapper`

* Make fake yxi align with vec-add memory widths

* Cleanup and add dynamic-wrapped-vec-add

* Get generated wrapper to run properly

* Add working generated wrapper + vec_add

Issue before was the vec_add was wrong, we need 4 bits instead of 3,
even though we're counting 0-7 because of the presence of a <=
check (so we need to get to 8 for our while loop to terminate)

* remove redundant attributes argument in py_ast

* Add space to py_ast.py to pass runt tests

* rename read_en to content_en

* add runt test on generation of calyx-py axi wrapper

calyx-py/calyx/py_ast.py

@@ -89,7 +89,7 @@ def doc(self) -> str:
         ins = ", ".join([s.doc() for s in self.inputs])
         outs = ", ".join([s.doc() for s in self.outputs])
         latency_annotation = (
-                f"static<{self.latency}> " if self.latency is not None else ""
+            f"static<{self.latency}> " if self.latency is not None else ""
         )
         attribute_annotation = f"<{', '.join([f'{a.doc()}' for a in self.attributes])}>" if self.attributes else ""
         signature = f"{latency_annotation}component {self.name}{attribute_annotation}({ins}) -> ({outs})"

runt.toml

@@ -481,6 +481,13 @@ fud e {} -s verilog.cycle_limit 500 \
          --to dat -q
 """
 
+[[tests]]
+name = "calyx-py AXI wrapper generation"
+paths = ["yxi/axi-calyx/axi-generator.py"]
+cmd = """
+python3 {}
+"""
+
 ##### Xilinx Tests ######
 [[tests]]
 name = "AXI wrapper generation"