While witout a comb group

calyxir · Aug 16, 2023 · 6742d36 · 6742d36
1 parent 85c99d0
commit 6742d36
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/frontends/systolic-lang/gen-systolic.py b/frontends/systolic-lang/gen-systolic.py
@@ -858,7 +858,7 @@ def counter():
     # build the while loop with condition cond_reg.
     # num repeats = (top_length - 1) + (left_length - 1) + (top_depth - 1) + 5 + 1
     cond_reg_port = comp.get_cell("cond_reg").port("out")
-    while_loop = cb.while_(cond_reg_port, None, while_body)
+    while_loop = cb.while_(cond_reg_port, while_body)
 
     control.append(while_loop)