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@anshumanmohan
anshumanmohan committed Jul 25, 2023
2 parents c9036a2 + 4ba11c4 commit 46b9eb7
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Showing 7 changed files with 283 additions and 227 deletions.
7 changes: 7 additions & 0 deletions calyx-py/calyx/builder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -564,6 +564,13 @@ def port(self, name: str) -> ExprBuilder:
"""Build a port access expression."""
return ExprBuilder(ast.Atom(ast.CompPort(self._cell.id, name)))

def is_mem_d1(self) -> bool:
"""Check if the cell is a StdMemD1 cell."""
return (
isinstance(self._cell.comp, ast.CompInst)
and self._cell.comp.id == "std_mem_d1"
)

@classmethod
def unwrap_id(cls, obj):
if isinstance(obj, cls):
Expand Down
240 changes: 187 additions & 53 deletions calyx-py/calyx/builder_util.py
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Original file line number Diff line number Diff line change
@@ -1,66 +1,130 @@
# pylint: disable=import-error
import calyx.builder as cb


def insert_eq(comp: cb.ComponentBuilder, a, b, cell, width):
"""Inserts wiring into component {comp} to check if {a} == {b}.
1. Within {comp}, creates a combinational group called {cell}_group.
2. Within the group, creates a {cell} that checks equalities of {width}.
3. Puts the values {a} and {b} into {cell}.
4. Returns the equality-checking cell and the overall group.
"""
eq_cell = comp.eq(cell, width)
with comp.comb_group(f"{cell}_group") as eq_group:
eq_cell.left = a
eq_cell.right = b
return eq_cell, eq_group


def insert_neq(comp: cb.ComponentBuilder, a, b, cell, width):
"""Inserts wiring into component {comp} to check if {a} != {b}.
1. Within {comp}, creates a combinational group called {cell}_group.
2. Within the group, creates a {cell} that checks inequalities of {width}.
3. Puts the values {a} and {b} into {cell}.
4. Returns the inequality-checking cell and the overall group.
"""
neq_cell = comp.neq(cell, width)
with comp.comb_group(f"{cell}_group") as neq_group:
neq_cell.left = a
neq_cell.right = b
return neq_cell, neq_group


def insert_incr(comp: cb.ComponentBuilder, reg, cell):
"""Inserts wiring into component {comp} to increment {reg} by 1.
1. Within component {comp}, creates a group called cell_{group}.
2. Within {group}, adds a cell {cell} that computes sums.
3. Puts the values of {port} and 1 into {cell}.
4. Then puts the answer of the computation back into {port}.
4. Returns the group that does this.
def insert_comb_group(comp: cb.ComponentBuilder, left, right, cell, groupname):
"""Accepts a cell that performs some computation on values {left} and {right}.
Creates a combinational group {groupname} that wires up the cell with these ports.
Returns the cell and the combintational group.
"""
with comp.comb_group(groupname) as comb_group:
cell.left = left
cell.right = right
return cell, comb_group


def insert_eq(comp: cb.ComponentBuilder, left, right, cellname, width):
"""Inserts wiring into component {comp} to check if {left} == {right}.
<cellname> = std_eq(<width>);
...
comb group <cellname>_group {
<cellname>.left = <left>;
<cellname>.right = <right>;
}
Returns handles to the cell and the combinational group.
"""
eq_cell = comp.eq(cellname, width)
return insert_comb_group(comp, left, right, eq_cell, f"{cellname}_group")


def insert_neq(comp: cb.ComponentBuilder, left, right, cellname, width):
"""Inserts wiring into component {comp} to check if {left} != {right}.
<cellname> = std_neq(<width>);
...
comb group <cellname>_group {
<cellname>.left = <left>;
<cellname>.right = <right>;
}
Returns handles to the cell and the combinational group.
"""
neq_cell = comp.neq(cellname, width)
return insert_comb_group(comp, left, right, neq_cell, f"{cellname}_group")


def insert_lt(comp: cb.ComponentBuilder, left, right, cellname, width):
"""Inserts wiring into component {comp} to check if {left} < {right}.
<cellname> = std_lt(<width>);
...
comb group <cellname>_group {
<cellname>.left = <left>;
<cellname>.right = <right>;
}
Returns handles to the cell and the combinational group.
"""
lt_cell = comp.lt(cellname, width)
return insert_comb_group(comp, left, right, lt_cell, f"{cellname}_group")


def insert_add(comp: cb.ComponentBuilder, left, right, cellname, width):
"""Inserts wiring into component {comp} to compute {left} + {right}.
<cellname> = std_add(<width>);
...
comb group <cellname>_group {
<cellname>.left = <left>;
<cellname>.right = <right>;
}
Returns handles to the cell and the combinational group.
"""
add_cell = comp.add(cellname, width)
return insert_comb_group(comp, left, right, add_cell, f"{cellname}_group")


def insert_sub(comp: cb.ComponentBuilder, left, right, cellname, width):
"""Inserts wiring into component {comp} to compute {left} - {right}.
<cellname> = std_sub(<width>);
...
comb group <cellname>_group {
<cellname>.left = <left>;
<cellname>.right = <right>;
}
Returns handles to the cell and the combinational group.
"""
sub_cell = comp.sub(cellname, width)
return insert_comb_group(comp, left, right, sub_cell, f"{cellname}_group")


def insert_incr(comp: cb.ComponentBuilder, reg, cellname, val=1):
"""Inserts wiring into component {comp} to increment register {reg} by {val}.
1. Within component {comp}, creates a group called {cellname}_group.
2. Within the group, adds a cell {cellname} that computes sums.
3. Puts the values {reg} and {val} into the cell.
4. Then puts the answer of the computation back into {reg}.
5. Returns the group that does this.
"""
incr_cell = comp.add(cell, 32)
with comp.group(f"{cell}group") as incr_group:
incr_cell.left = reg.out
incr_cell.right = cb.const(32, 1)
add_cell = comp.add(cellname, 32)
with comp.group(f"{cellname}_group") as incr_group:
add_cell.left = reg.out
add_cell.right = cb.const(32, val)
reg.write_en = 1
reg.in_ = incr_cell.out
reg.in_ = add_cell.out
incr_group.done = reg.done
return incr_group


def insert_decr(comp: cb.ComponentBuilder, reg, cell):
"""Inserts wiring into component {comp} to decrement {reg} by 1.
1. Within component {comp}, creates a group called {group}.
2. Within {group}, adds a cell {cell} that computes differences.
3. Puts the values of {port} and 1 into {cell}.
4. Then puts the answer of the computation back into {port}.
4. Returns the group that does this.
def insert_decr(comp: cb.ComponentBuilder, reg, cellname, val=1):
"""Inserts wiring into component {comp} to decrement register {reg} by {val}.
1. Within component {comp}, creates a group called {cellname}_group.
2. Within the group, adds a cell {cellname} that computes differences.
3. Puts the values {reg} and {val} into the cell.
4. Then puts the answer of the computation back into {reg}.
5. Returns the group that does this.
"""
decr_cell = comp.sub(cell, 32)
with comp.group(f"{cell}group") as decr_group:
decr_cell.left = reg.out
decr_cell.right = cb.const(32, 1)
sub_cell = comp.sub(cellname, 32)
with comp.group(f"{cellname}_group") as decr_group:
sub_cell.left = reg.out
sub_cell.right = cb.const(32, val)
reg.write_en = 1
reg.in_ = decr_cell.out
reg.in_ = sub_cell.out
decr_group.done = reg.done
return decr_group

Expand Down Expand Up @@ -95,7 +159,7 @@ def mem_store(comp: cb.ComponentBuilder, mem, i, val, group):
return store_grp


def reg_store(comp: cb.ComponentBuilder, reg, val, group):
def insert_reg_store(comp: cb.ComponentBuilder, reg, val, group):
"""Stores a value in a register.
1. Within component {comp}, creates a group called {group}.
2. Within {group}, sets the register {reg} to {val}.
Expand Down Expand Up @@ -166,3 +230,73 @@ def reg_swap(comp: cb.ComponentBuilder, a, b, group):
b.in_ = tmp.out
swap_grp.done = b.done
return swap_grp


def insert_mem_load_to_mem(comp: cb.ComponentBuilder, mem, i, ans, j, group):
"""Loads a value from one std_mem_d1 memory into another.
1. Within component {comp}, creates a group called {group}.
2. Within {group}, reads from memory {mem} at address {i}.
3. Writes the value into memory {ans} at address {j}.
4. Returns the group that does this.
"""
assert mem.is_mem_d1() and ans.is_mem_d1()
with comp.group(group) as load_grp:
mem.addr0 = i
ans.write_en = 1
ans.addr0 = j
ans.write_data = mem.read_data
load_grp.done = ans.done
return load_grp


def insert_add_store_in_reg(
comp: cb.ComponentBuilder,
cellname,
left,
right,
ans_reg=None,
):
"""Inserts wiring into component {comp} to compute {left} + {right} and
store it in {ans_reg}.
1. Within component {comp}, creates a group called {cellname}_group.
2. Within {group}, create a cell {cellname} that computes sums.
3. Puts the values of {left} and {right} into the cell.
4. Then puts the answer of the computation into {ans_reg}.
4. Returns the summing group and the register.
"""
add_cell = comp.add(cellname, 32)
ans_reg = ans_reg or comp.reg(f"reg_{cellname}", 32)
with comp.group(f"{cellname}_group") as adder_group:
add_cell.left = left
add_cell.right = right
ans_reg.write_en = 1
ans_reg.in_ = add_cell.out
adder_group.done = ans_reg.done
return adder_group, ans_reg


def insert_sub_store_in_reg(
comp: cb.ComponentBuilder,
left,
right,
cellname,
width,
ans_reg=None,
):
"""Adds wiring into component {comp} to compute {left} - {right}
and store it in {ans_reg}.
1. Within component {comp}, creates a group called {cellname}_group.
2. Within {group}, create a cell {cellname} that computes differences.
3. Puts the values of {left} and {right} into {cell}.
4. Then puts the answer of the computation into {ans_reg}.
4. Returns the subtracting group and the register.
"""
sub_cell = comp.sub(cellname, width)
ans_reg = ans_reg or comp.reg(f"reg_{cellname}", width)
with comp.group(f"{cellname}_group") as sub_group:
sub_cell.left = left
sub_cell.right = right
ans_reg.write_en = 1
ans_reg.in_ = sub_cell.out
sub_group.done = ans_reg.done
return sub_group, ans_reg
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