define ir::rrc to build RRCs (#1710)

calyxir · Aug 31, 2023 · 40f54c8 · 40f54c8
1 parent 4ceff9c
commit 40f54c8
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Showing 11 changed files with 34 additions and 36 deletions.
diff --git a/calyx-ir/src/builder.rs b/calyx-ir/src/builder.rs
@@ -2,7 +2,6 @@
 //! representation.
 use crate::{self as ir, LibrarySignatures, Nothing, RRC, WRC};
 use calyx_frontend::BoolAttr;
-use std::cell::RefCell;
 use std::rc::Rc;
 
 use super::{CellType, PortDef};
@@ -75,17 +74,17 @@ impl<'a> Builder<'a> {
         let name = self.component.generate_name(prefix);
 
         // Check if there is a group with the same name.
-        let group = Rc::new(RefCell::new(ir::Group::new(name)));
+        let group = ir::rrc(ir::Group::new(name));
 
         // Add default holes to the group.
         for (name, width) in &[("go", 1), ("done", 1)] {
-            let hole = Rc::new(RefCell::new(ir::Port {
+            let hole = ir::rrc(ir::Port {
                 name: ir::Id::from(*name),
                 width: *width,
                 direction: ir::Direction::Inout,
                 parent: ir::PortParent::Group(WRC::from(&group)),
                 attributes: ir::Attributes::default(),
-            }));
+            });
             group.borrow_mut().holes.push(hole);
         }
 
@@ -114,19 +113,19 @@ impl<'a> Builder<'a> {
         let name = self.component.generate_name(prefix);
 
         // Check if there is a group with the same name.
-        let group = Rc::new(RefCell::new(ir::StaticGroup::new(name, latency)));
+        let group = ir::rrc(ir::StaticGroup::new(name, latency));
 
         // Add default holes to the group.
         // Static Groups don't need a done hole.
         // May be beneficial to have a go hole, though (although maybe not)
         let (name, width) = ("go", 1);
-        let hole = Rc::new(RefCell::new(ir::Port {
+        let hole = ir::rrc(ir::Port {
             name: ir::Id::from(name),
             width,
             direction: ir::Direction::Inout,
             parent: ir::PortParent::StaticGroup(WRC::from(&group)),
             attributes: ir::Attributes::default(),
-        }));
+        });
         group.borrow_mut().holes.push(hole);
 
         // Add the group to the component.
@@ -145,11 +144,11 @@ impl<'a> Builder<'a> {
         let name = self.component.generate_name(prefix);
 
         // Check if there is a group with the same name.
-        let group = Rc::new(RefCell::new(ir::CombGroup {
+        let group = ir::rrc(ir::CombGroup {
             name,
             attributes: ir::Attributes::default(),
             assignments: vec![],
-        }));
+        });
 
         // Add the group to the component.
         self.component.comb_groups.add(Rc::clone(&group));
@@ -346,15 +345,15 @@ impl<'a> Builder<'a> {
         typ: ir::CellType,
         ports: Vec<ir::PortDef<u64>>,
     ) -> RRC<ir::Cell> {
-        let cell = Rc::new(RefCell::new(ir::Cell::new(name, typ)));
+        let cell = ir::rrc(ir::Cell::new(name, typ));
         ports.into_iter().for_each(|pd| {
-            let port = Rc::new(RefCell::new(ir::Port {
+            let port = ir::rrc(ir::Port {
                 name: pd.name(),
                 width: pd.width,
                 direction: pd.direction,
                 parent: ir::PortParent::Cell(WRC::from(&cell)),
                 attributes: pd.attributes,
-            }));
+            });
             cell.borrow_mut().ports.push(port);
         });
         cell

diff --git a/calyx-ir/src/common.rs b/calyx-ir/src/common.rs
@@ -8,6 +8,11 @@ use std::rc::{Rc, Weak};
 #[allow(clippy::upper_case_acronyms)]
 pub type RRC<T> = Rc<RefCell<T>>;
 
+/// Construct a new RRC.
+pub fn rrc<T>(t: T) -> RRC<T> {
+    Rc::new(RefCell::new(t))
+}
+
 /// A Wrapper for a weak RefCell pointer.
 /// Used by parent pointers in the internal representation.
 #[allow(clippy::upper_case_acronyms)]

diff --git a/calyx-ir/src/component.rs b/calyx-ir/src/component.rs
@@ -8,7 +8,6 @@ use crate::Nothing;
 use calyx_utils::NameGenerator;
 use itertools::Itertools;
 use linked_hash_map::LinkedHashMap;
-use std::cell::RefCell;
 use std::collections::HashSet;
 use std::iter::Extend;
 use std::num::NonZeroU64;
@@ -135,7 +134,7 @@ impl Component {
             static_groups: IdList::default(),
             comb_groups: IdList::default(),
             continuous_assignments: vec![],
-            control: Rc::new(RefCell::new(Control::empty())),
+            control: super::rrc(Control::empty()),
             namegen: NameGenerator::with_prev_defined_names(prev_names),
             attributes: Attributes::default(),
             is_comb,

diff --git a/calyx-ir/src/from_ast.rs b/calyx-ir/src/from_ast.rs
@@ -8,7 +8,6 @@ use crate::{Nothing, PortComp, StaticTiming};
 use calyx_frontend::{ast, ast::Atom, BoolAttr, Workspace};
 use calyx_utils::{CalyxResult, Error, GPosIdx, WithPos};
 use itertools::Itertools;
-use std::cell::RefCell;
 
 use std::collections::{HashMap, HashSet};
 use std::num::NonZeroU64;
@@ -287,11 +286,8 @@ fn build_component(
     builder.component.continuous_assignments = continuous_assignments;
 
     // Build the Control ast using ast::Control.
-    let control = Rc::new(RefCell::new(build_control(
-        comp.control,
-        sig_ctx,
-        &mut builder,
-    )?));
+    let control =
+        super::rrc(build_control(comp.control, sig_ctx, &mut builder)?);
 
     builder.component.control = control;
 

diff --git a/calyx-ir/src/lib.rs b/calyx-ir/src/lib.rs
@@ -24,7 +24,7 @@ pub mod rewriter;
 // Re-export types at the module level.
 pub use builder::Builder;
 pub use calyx_utils::{GetName, Id};
-pub use common::{RRC, WRC};
+pub use common::{rrc, RRC, WRC};
 pub use component::{Component, IdList};
 pub use context::{BackendConf, Context};
 pub use control::{

diff --git a/calyx-opt/src/passes/compile_invoke.rs b/calyx-opt/src/passes/compile_invoke.rs
@@ -6,7 +6,6 @@ use calyx_ir::{self as ir, Attributes, LibrarySignatures};
 use calyx_utils::{CalyxResult, Error};
 use ir::{RRC, WRC};
 use itertools::Itertools;
-use std::cell::RefCell;
 use std::collections::HashMap;
 use std::rc::Rc;
 
@@ -245,13 +244,13 @@ impl Visitor for CompileInvoke {
                         cell.borrow().name()
                     );
                     for p in vec.iter() {
-                        let new_port = Rc::new(RefCell::new(ir::Port {
+                        let new_port = ir::rrc(ir::Port {
                             name: p.borrow().name,
                             width: p.borrow().width,
                             direction: p.borrow().direction.reverse(),
                             parent: ir::PortParent::Cell(WRC::from(cell)),
                             attributes: Attributes::default(),
-                        }));
+                        });
                         new_ports.push(new_port);
                     }
                 }

diff --git a/calyx-opt/src/passes/dump_ports.rs b/calyx-opt/src/passes/dump_ports.rs
@@ -1,7 +1,7 @@
 use calyx_ir::{self as ir, RRC, WRC};
 use ir::rewriter;
 use itertools::Itertools;
-use std::{cell::RefCell, rc::Rc};
+use std::rc::Rc;
 
 #[derive(Default)]
 /// Results generated from the process of dumping out ports.
@@ -62,13 +62,13 @@ where
         for port_ref in ports_inline {
             let canon = port_ref.borrow().canonical();
             let port = port_ref.borrow();
-            let new_port = Rc::new(RefCell::new(ir::Port {
+            let new_port = ir::rrc(ir::Port {
                 name: component.generate_name(format_port_name(&canon)),
                 width: port.width,
                 direction: port.direction.clone(),
                 parent: ir::PortParent::Cell(WRC::from(&component.signature)),
                 attributes: ir::Attributes::default(),
-            }));
+            });
             component
                 .signature
                 .borrow_mut()

diff --git a/calyx-opt/src/passes/top_down_static_timing/tdst.rs b/calyx-opt/src/passes/top_down_static_timing/tdst.rs
@@ -10,7 +10,6 @@ use calyx_ir::{
 use calyx_utils::{CalyxResult, Error};
 use ir::Nothing;
 use itertools::Itertools;
-use std::cell::RefCell;
 use std::collections::{HashMap, HashSet};
 use std::io::Write;
 use std::iter;
@@ -910,7 +909,7 @@ impl Visitor for TopDownStaticTiming {
         Self::compile_sub_programs(&mut con, &mut builder, self.dump_fsm)?;
 
         // Add the control program back.
-        comp.control = Rc::new(RefCell::new(con));
+        comp.control = ir::rrc(con);
 
         // If the force flag is set, make sure that we only have one group remaining
         if self.force

diff --git a/interp/src/structures/environment.rs b/interp/src/structures/environment.rs
@@ -17,7 +17,6 @@ use crate::{
     values::Value,
 };
 use calyx_ir::{self as ir, RRC};
-use std::cell::RefCell;
 use std::collections::{HashMap, HashSet};
 use std::iter::once;
 use std::rc::Rc;
@@ -488,7 +487,7 @@ impl InterpreterState {
                 _ => {}
             }
         }
-        Ok((Rc::new(RefCell::new(map)), set))
+        Ok((ir::rrc(map), set))
     }
 
     /// A helper meathod which constructs the initial environment map from ports

diff --git a/interp/src/structures/values.rs b/interp/src/structures/values.rs
@@ -9,6 +9,8 @@ use itertools::Itertools;
 use serde::de::{self, Deserialize, Visitor};
 use serde::Serialize;
 
+use calyx_ir as ir;
+
 pub type BitString = BitVec<usize, Lsb0>;
 
 /// Retrieves the unsigned fixed point representation of `v`. This splits the representation into
@@ -333,8 +335,8 @@ impl Value {
         let input_num: InputNumber = bitwidth.into();
         Value {
             vec: Rc::new(bitvec![usize, Lsb0; 0; input_num.as_usize()]),
-            unsigned: Rc::new(RefCell::new(Some(0_u8.into()))),
-            signed: Rc::new(RefCell::new(Some(0.into()))),
+            unsigned: ir::rrc(Some(0_u8.into())),
+            signed: ir::rrc(Some(0.into())),
         }
     }
 
@@ -383,8 +385,8 @@ impl Value {
         (
             Value {
                 vec: Rc::new(bv),
-                signed: Rc::new(RefCell::new(None)),
-                unsigned: Rc::new(RefCell::new(None)),
+                signed: ir::rrc(None),
+                unsigned: ir::rrc(None),
             },
             flag,
         )

diff --git a/tests/errors/insufficient-params.expect b/tests/errors/insufficient-params.expect
@@ -1,5 +1,5 @@
 ---CODE---
 101
 ---STDERR---
-thread 'main' panicked at 'Failed to add primitive.: Malformed Structure: Invalid parameter binding for primitive `std_fp_div_pipe`. Requires 3 parameters but provided with 1.', calyx-ir/src/builder.rs:220:14
+thread 'main' panicked at 'Failed to add primitive.: Malformed Structure: Invalid parameter binding for primitive `std_fp_div_pipe`. Requires 3 parameters but provided with 1.', calyx-ir/src/builder.rs:219:14
 note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace