Skip to content

Commit

Permalink
update changelog
Browse files Browse the repository at this point in the history
  • Loading branch information
rachitnigam committed Aug 11, 2023
1 parent 63ea472 commit 0abc212
Showing 1 changed file with 1 addition and 0 deletions.
1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
## Unreleased
- Don't require `@clk` and `@reset` ports in `comb` components
- `inline` pass supports inlining `ref` cells
- `comb-prop`: disable rewrite from `wire.in = port` when the output of a wire is read.


## 0.4.0
Expand Down

0 comments on commit 0abc212

Please sign in to comment.