Fix: warning pedantic empty init

src/platforms/hosted/cli.c

@@ -103,7 +103,7 @@ static bool bmp_mmap(char *file, mmap_data_s *map)
 		DEBUG_ERROR("Open file %s failed: %s\n", file, strerror(errno));
 		return false;
 	}
-	struct stat stat = {};
+	struct stat stat = {0};
 	if (fstat(map->fd, &stat))
 		return false;
 	map->real_size = stat.st_size;
@@ -533,7 +533,7 @@ int cl_execute(bmda_cli_options_s *opt)
 	if (opt->opt_mode == BMP_MODE_TEST || opt->opt_mode == BMP_MODE_SWJ_TEST)
 		goto target_detach;
 
-	mmap_data_s map = {};
+	mmap_data_s map = {0};
 	if (opt->opt_mode == BMP_MODE_FLASH_WRITE || opt->opt_mode == BMP_MODE_FLASH_VERIFY ||
 		opt->opt_mode == BMP_MODE_FLASH_WRITE_VERIFY) {
 		if (!bmp_mmap(opt->opt_flash_file, &map)) {

src/platforms/hosted/cmsis_dap.c

@@ -276,7 +276,7 @@ bool dap_init(void)
 
 dap_version_s dap_adaptor_version(const dap_info_e version_kind)
 {
-	char version_str[256U] = {};
+	char version_str[256U] = {0};
 	/* Try to retrieve the version string, and if we fail, report back an obvious bad one */
 	const size_t version_length = dap_info(version_kind, version_str, ARRAY_LENGTH(version_str));
 	if (!version_length)
@@ -289,7 +289,7 @@ dap_version_s dap_adaptor_version(const dap_info_e version_kind)
 		DEBUG_INFO("CMSIS-DAP v%s\n", version_str);
 	const char *begin = version_str;
 	char *end = NULL;
-	dap_version_s version = {};
+	dap_version_s version = {0};
 	/* If the string starts with a 'v' or 'V', skip over that */
 	if (begin[0] == 'v' || begin[0] == 'V')
 		++begin;

src/platforms/hosted/dap_command.c

@@ -148,7 +148,7 @@ bool perform_dap_transfer_block_read(
 	dap_transfer_block_request_read_s request = {
 		DAP_TRANSFER_BLOCK,
 		target_dp->dev_index,
-		{},
+		{0},
 		reg | DAP_TRANSFER_RnW,
 	};
 	write_le2(request.block_count, 0, block_count);
@@ -184,7 +184,7 @@ bool perform_dap_transfer_block_write(
 	dap_transfer_block_request_write_s request = {
 		DAP_TRANSFER_BLOCK,
 		target_dp->dev_index,
-		{},
+		{0},
 		reg & ~DAP_TRANSFER_RnW,
 	};
 	write_le2(request.block_count, 0, block_count);

src/platforms/hosted/dap_jtag.c

@@ -87,7 +87,7 @@ static void dap_jtag_reset(void)
 
 static void dap_jtag_tms_seq(const uint32_t tms_states, const size_t clock_cycles)
 {
-	uint8_t sequence[4] = {};
+	uint8_t sequence[4] = {0};
 	write_le4(sequence, 0, tms_states);
 	perform_dap_swj_sequence(clock_cycles, sequence);
 	DEBUG_PROBE("jtagtap_tms_seq data_in %08x %zu\n", tms_states, clock_cycles);

src/platforms/hosted/dap_swd.c

@@ -204,7 +204,7 @@ static bool dap_write_reg_no_check(uint16_t addr, const uint32_t data)
 		/* Perform one turn-around cycle then read the 3 bit ACK */
 		{4U, DAP_SWD_IN_SEQUENCE},
 		/* Perform another turnaround cycle */
-		{1U, DAP_SWD_OUT_SEQUENCE, {}},
+		{1U, DAP_SWD_OUT_SEQUENCE, {0}},
 		/* Now write out the 32b of data to send and the 1b of parity */
 		{
 			33U,

src/platforms/hosted/ftdi_bmp.c

@@ -376,7 +376,7 @@ const cable_desc_s cable_desc[] = {
 		.name = "arm-usb-tiny-h",
 		.description = "Olimex OpenOCD JTAG ARM-USB-TINY-H",
 	},
-	{},
+	{0},
 };
 
 /*

src/platforms/hosted/ftdi_swd.c

@@ -147,7 +147,7 @@ static void ftdi_swd_turnaround_mpsse(const swdio_status_e dir)
 		ftdi_buffer_write_arr(cmd_read);
 	}
 	/* Run one idle clock cycle */
-	const ftdi_mpsse_cmd_s cmd = {MPSSE_TDO_SHIFT, {}};
+	const ftdi_mpsse_cmd_s cmd = {MPSSE_TDO_SHIFT, {0}};
 	ftdi_buffer_write_val(cmd);
 	/* If the turnaround should set SWDIO to an output */
 	if (dir == SWDIO_STATUS_DRIVE) {
@@ -234,7 +234,7 @@ static void ftdi_swd_turnaround(const swdio_status_e dir)
 
 static bool ftdi_swd_seq_in_parity_mpsse(uint32_t *const result, const size_t clock_cycles)
 {
-	uint8_t data_out[5] = {};
+	uint8_t data_out[5U] = {0};
 	ftdi_jtag_tdi_tdo_seq(data_out, false, NULL, clock_cycles + 1U);
 	const uint32_t data = read_le4(data_out, 0);
 	uint8_t parity = __builtin_parity(data & ((UINT64_C(1) << clock_cycles) - 1U));
@@ -338,7 +338,7 @@ static void ftdi_swd_seq_out_mpsse(const uint32_t tms_states, const size_t clock
 static void ftdi_swd_seq_out_raw(uint32_t tms_states, const size_t clock_cycles)
 {
 	DEBUG_PROBE("%s %zu clock_cycles: %08" PRIx32 "\n", __func__, clock_cycles, tms_states);
-	uint8_t cmd[15] = {};
+	uint8_t cmd[15U] = {0};
 	size_t offset = 0U;
 	for (size_t cycle = 0U; cycle < clock_cycles; cycle += 7U, offset += 3U) {
 		const size_t cycles = MIN(7U, clock_cycles - cycle);
@@ -391,7 +391,7 @@ static void ftdi_swd_seq_out_parity_mpsse(const uint32_t tms_states, const uint8
 static void ftdi_swd_seq_out_parity_raw(const uint32_t tms_states, const uint8_t parity, const size_t clock_cycles)
 {
 	DEBUG_PROBE("%s %zu clock_cycles: %08" PRIx32 "\n", __func__, clock_cycles, tms_states);
-	uint8_t cmd[18] = {};
+	uint8_t cmd[18U] = {0};
 	size_t offset = 0;
 	for (size_t cycle = 0U; cycle < clock_cycles; cycle += 7U, offset += 3U) {
 		const size_t cycles = MIN(7U, clock_cycles - cycle);

src/platforms/hosted/gdb_if.c

@@ -120,7 +120,7 @@ static inline uint16_t u16_to_be(const uint16_t value)
 
 static sockaddr_storage_s sockaddr_prepare(const uint16_t port)
 {
-	addrinfo_s hints = {};
+	addrinfo_s hints = {0};
 	/* Use AF_UNSPEC here to support either IPv4 or v6 */
 	hints.ai_family = AF_UNSPEC;
 	/* Ask for a normal TCP socket */
@@ -218,7 +218,7 @@ static void socket_set_flags(const socket_t socket, const int flags)
 int gdb_if_init(void)
 {
 #if defined(_WIN32) || defined(__CYGWIN__)
-	WSADATA wsa_data = {};
+	WSADATA wsa_data = {0};
 	const int result = WSAStartup(MAKEWORD(2, 2), &wsa_data);
 	if (result != NO_ERROR) {
 		DEBUG_ERROR("WSAStartup failed with error: %d\n", result);

src/platforms/hosted/serial_win.c

@@ -186,7 +186,7 @@ bool serial_open(const bmda_cli_options_s *const cl_opts, const char *const seri
 		return false;
 	}
 
-	DCB serial_params = {};
+	DCB serial_params = {0};
 	serial_params.DCBlength = sizeof(serial_params);
 	if (!GetCommState(port_handle, &serial_params)) {
 		handle_dev_error(port_handle, "getting communication state from device");
@@ -208,7 +208,7 @@ bool serial_open(const bmda_cli_options_s *const cl_opts, const char *const seri
 		return false;
 	}
 
-	COMMTIMEOUTS timeouts = {};
+	COMMTIMEOUTS timeouts = {0};
 	timeouts.ReadIntervalTimeout = 10;
 	timeouts.ReadTotalTimeoutConstant = 10;
 	timeouts.ReadTotalTimeoutMultiplier = 10;

src/remote.c

@@ -59,7 +59,7 @@ uint64_t remote_hex_string_to_num(const uint32_t max, const char *const str)
 /* hex-ify and send a buffer of data */
 static void remote_send_buf(const void *const buffer, const size_t len)
 {
-	char hex[2] = {};
+	char hex[2] = {0};
 	const uint8_t *const data = (const uint8_t *)buffer;
 	for (size_t offset = 0; offset < len; ++offset) {
 		hexify(hex, data + offset, 1U);
@@ -332,7 +332,7 @@ static void remote_packet_process_high_level(const char *packet, const size_t pa
 			break;
 		}
 
-		jtag_dev_s jtag_dev = {};
+		jtag_dev_s jtag_dev = {0};
 		const uint8_t index = remote_hex_string_to_num(2, packet + 2);
 		jtag_dev.dr_prescan = remote_hex_string_to_num(2, packet + 4);
 		jtag_dev.dr_postscan = remote_hex_string_to_num(2, packet + 6);
@@ -605,7 +605,7 @@ void remote_packet_process(unsigned i, char *packet)
 
 	case REMOTE_ADIv5_PACKET: {
 		/* Setup an exception frame to try the ADIv5 operation in */
-		volatile exception_s error = {};
+		volatile exception_s error = {0};
 		TRY_CATCH (error, EXCEPTION_ALL) {
 			remote_packet_process_adiv5(packet, i);
 		}

src/target/adiv5.c

@@ -691,7 +691,7 @@ adiv5_access_port_s *adiv5_new_ap(adiv5_debug_port_s *dp, uint8_t apsel)
 		return NULL;
 #endif
 
-	adiv5_access_port_s tmpap = {};
+	adiv5_access_port_s tmpap = {0};
 	/* Assume valid and try to read IDR */
 	tmpap.dp = dp;
 	tmpap.apsel = apsel;

src/target/imxrt.c

@@ -322,7 +322,7 @@ static uint8_t imxrt_spi_build_insn_sequence(target_s *const target, const uint1
 		slot = 0;
 
 	/* Build a new microcode sequence to run */
-	imxrt_flexspi_lut_insn_s sequence[8] = {};
+	imxrt_flexspi_lut_insn_s sequence[8] = {0};
 	/* Start by writing the command opcode to the Flash */
 	sequence[0].opcode_mode = IMXRT_FLEXSPI_LUT_OPCODE(IMXRT_FLEXSPI_LUT_OP_COMMAND) | IMXRT_FLEXSPI_LUT_MODE_SERIAL;
 	sequence[0].value = command & SPI_FLASH_OPCODE_MASK;
@@ -427,7 +427,7 @@ static void imxrt_spi_write(target_s *const target, const uint16_t command, cons
 			target_mem_read32(target, IMXRT_FLEXSPI1_PRG_WRITE_FIFO_STATUS) & IMXRT_FLEXSPI1_PRG_WRITE_FIFO_STATUS_FILL)
 			continue;
 		const uint16_t amount = MIN(128U, (uint16_t)(length - offset));
-		uint32_t data[32] = {};
+		uint32_t data[32] = {0};
 		memcpy(data, (const char *)buffer + offset, amount);
 		target_mem_write(target, IMXRT_FLEXSPI1_PRG_WRITE_FIFO, data, (amount + 3U) & ~3U);
 		/* Tell the controller we've filled the write FIFO */

src/target/jtag_scan.c

@@ -211,7 +211,7 @@ static jtag_ir_quirks_s jtag_device_get_quirks(const uint32_t idcode)
 		if ((idcode & dev_descr[idx].idmask) == dev_descr[idx].idcode)
 			return dev_descr[idx].ir_quirks;
 	}
-	return (jtag_ir_quirks_s){};
+	return (jtag_ir_quirks_s){0};
 }
 
 static bool jtag_read_irs(void)

src/target/lpc11xx.c

@@ -308,10 +308,10 @@ static bool lpc11xx_read_uid(target_s *target, int argc, const char **argv)
 	(void)argc;
 	(void)argv;
 	lpc_flash_s *flash = (lpc_flash_s *)target->flash;
-	iap_result_s result = {};
+	iap_result_s result = {0};
 	if (lpc_iap_call(flash, &result, IAP_CMD_READUID))
 		return false;
-	uint8_t uid[16] = {};
+	uint8_t uid[16U] = {0};
 	memcpy(&uid, result.values, sizeof(uid));
 	tc_printf(target, "UID: 0x");
 	for (size_t i = 0; i < sizeof(uid); ++i)

src/target/lpc15xx.c

@@ -41,10 +41,10 @@ static bool lpc15xx_read_uid(target_s *target, int argc, const char *argv[])
 	(void)argc;
 	(void)argv;
 	struct lpc_flash *flash = (struct lpc_flash *)target->flash;
-	iap_result_s result = {};
+	iap_result_s result = {0};
 	if (lpc_iap_call(flash, &result, IAP_CMD_READUID))
 		return false;
-	uint8_t uid[16] = {};
+	uint8_t uid[16U] = {0};
 	memcpy(&uid, result.values, sizeof(uid));
 	tc_printf(target, "UID: 0x");
 	for (uint32_t i = 0; i < sizeof(uid); ++i)

src/target/lpc546xx.c

@@ -217,10 +217,10 @@ static bool lpc546xx_cmd_read_uid(target_s *target, int argc, const char **argv)
 	(void)argc;
 	(void)argv;
 	lpc_flash_s *flash = (lpc_flash_s *)target->flash;
-	iap_result_s result = {};
+	iap_result_s result = {0};
 	if (lpc_iap_call(flash, &result, IAP_CMD_READUID))
 		return false;
-	uint8_t uid[16] = {};
+	uint8_t uid[16U] = {0};
 	memcpy(&uid, result.values, sizeof(uid));
 	tc_printf(target, "UID: 0x");
 	for (uint32_t i = 0; i < sizeof(uid); ++i)

src/target/lpc55xx.c

@@ -529,7 +529,7 @@ void lpc55_dp_prepare(adiv5_debug_port_s *const dp)
 	 */
 	adiv5_dp_abort(dp, ADIV5_DP_ABORT_DAPABORT);
 	/* Set up a dummy Access Port on the stack */
-	adiv5_access_port_s ap = {};
+	adiv5_access_port_s ap = {0};
 	ap.dp = dp;
 	ap.apsel = 2;
 	/* Read out the ID register and check it's the LPC55's Debug Mailbox ID */

src/target/lpc_common.c

@@ -244,7 +244,7 @@ iap_status_e lpc_iap_call(lpc_flash_s *const flash, iap_result_s *const result,
 	}
 
 	/* Copy back just the results */
-	iap_result_s results = {};
+	iap_result_s results = {0};
 	target_mem_read(target, &results, iap_results_addr, sizeof(iap_result_s));
 
 	/* Restore the original data in RAM and registers */

src/target/nrf51.c

@@ -115,7 +115,7 @@ static void nrf51_add_flash(target_s *t, uint32_t addr, size_t length, size_t er
 	f->length = length;
 	f->blocksize = erasesize;
 	/* Limit the write buffer size to 1k to help prevent probe memory exhaustion */
-	f->writesize = MIN(erasesize, 1024);
+	f->writesize = MIN(erasesize, 1024U);
 	f->erase = nrf51_flash_erase;
 	f->write = nrf51_flash_write;
 	f->prepare = nrf51_flash_prepare;
@@ -144,7 +144,7 @@ bool nrf51_probe(target_s *t)
 		uint32_t ram_size = target_mem_read32(t, NRF52_INFO_RAM);
 		t->driver = "Nordic nRF52";
 		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
-		target_add_ram(t, 0x20000000, ram_size * 1024U);
+		target_add_ram(t, 0x20000000U, ram_size * 1024U);
 		nrf51_add_flash(t, 0, page_size * code_size, page_size);
 		nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
 		target_add_commands(t, nrf51_cmd_list, "nRF52");
@@ -154,7 +154,7 @@ bool nrf51_probe(target_s *t)
 		 * Use the biggest RAM size seen in NRF51 fammily.
 		 * IDCODE is kept as '0', as deciphering is hard and there is later no usage.
 		 */
-		target_add_ram(t, 0x20000000, 0x8000);
+		target_add_ram(t, 0x20000000U, 0x8000U);
 		t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
 		nrf51_add_flash(t, 0, page_size * code_size, page_size);
 		nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
@@ -205,7 +205,7 @@ static bool nrf51_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
 		/* If the address to erase is the UICR, we have to handle that separately */
 		if (addr + offset == NRF51_UICR)
 			/* Write to the ERASE_UICR register to erase */
-			target_mem_write32(t, NRF51_NVMC_ERASEUICR, 0x1);
+			target_mem_write32(t, NRF51_NVMC_ERASEUICR, 0x1U);
 		else
 			/* Write address of first word in page to erase it */
 			target_mem_write32(t, NRF51_NVMC_ERASEPAGE, addr + offset);
@@ -234,10 +234,10 @@ static bool nrf51_mass_erase(target_s *t)
 	if (!nrf51_wait_ready(t, NULL))
 		return false;
 
-	platform_timeout_s timeout = {};
-	platform_timeout_set(&timeout, 500);
+	platform_timeout_s timeout;
+	platform_timeout_set(&timeout, 500U);
 	/* Erase all */
-	target_mem_write32(t, NRF51_NVMC_ERASEALL, 1);
+	target_mem_write32(t, NRF51_NVMC_ERASEALL, 1U);
 	return nrf51_wait_ready(t, &timeout);
 }
 
@@ -253,7 +253,7 @@ static bool nrf51_cmd_erase_uicr(target_s *t, int argc, const char **argv)
 		return false;
 
 	/* Erase UICR */
-	target_mem_write32(t, NRF51_NVMC_ERASEUICR, 1);
+	target_mem_write32(t, NRF51_NVMC_ERASEUICR, 1U);
 	return nrf51_wait_ready(t, NULL);
 }
 
@@ -268,7 +268,7 @@ static bool nrf51_cmd_protect_flash(target_s *t, int argc, const char **argv)
 	if (!nrf51_wait_ready(t, NULL))
 		return false;
 
-	target_mem_write32(t, NRF51_APPROTECT, 0xffffff00);
+	target_mem_write32(t, NRF51_APPROTECT, 0xffffff00U);
 	return nrf51_wait_ready(t, NULL);
 }
 
@@ -441,12 +441,12 @@ static bool nrf51_mdm_mass_erase(target_s *t)
 	adiv5_access_port_s *ap = t->priv;
 
 	uint32_t status = adiv5_ap_read(ap, MDM_STATUS);
-	adiv5_dp_write(ap->dp, MDM_POWER_EN, 0x50000000);
-	adiv5_dp_write(ap->dp, MDM_SELECT_AP, 0x01000000);
-	adiv5_ap_write(ap, MDM_CONTROL, 0x00000001);
+	adiv5_dp_write(ap->dp, MDM_POWER_EN, 0x50000000U);
+	adiv5_dp_write(ap->dp, MDM_SELECT_AP, 0x01000000U);
+	adiv5_ap_write(ap, MDM_CONTROL, 0x00000001U);
 
 	platform_timeout_s timeout;
-	platform_timeout_set(&timeout, 500);
+	platform_timeout_set(&timeout, 500U);
 	// Read until 0, probably should have a timeout here...
 	do {
 		status = adiv5_ap_read(ap, MDM_STATUS);

src/target/sam3x.c

@@ -298,7 +298,7 @@ static size_t sam_sram_size(uint32_t cidr)
 
 samx7x_descr_s samx7x_parse_id(uint32_t cidr, uint32_t exid)
 {
-	samx7x_descr_s descr = {};
+	samx7x_descr_s descr = {0};
 
 	switch (cidr & CHIPID_CIDR_ARCH_MASK) {
 	case CHIPID_CIDR_ARCH_SAME70:

src/target/samd.c

@@ -353,7 +353,7 @@ typedef struct samd_descr {
 
 samd_descr_s samd_parse_device_id(uint32_t did)
 {
-	samd_descr_s samd = {};
+	samd_descr_s samd = {0};
 	const samd_part_s *parts = samd_d21_parts;
 	samd.ram_size = 0x8000;
 	samd.flash_size = 0x40000;

src/target/samx5x.c

@@ -224,7 +224,7 @@ typedef struct samx5x_descr {
 
 samx5x_descr_s samx5x_parse_device_id(uint32_t did)
 {
-	samx5x_descr_s samd = {};
+	samx5x_descr_s samd = {0};
 
 	/* Series */
 	const uint8_t series = (did >> SAMX5X_DID_SERIES_POS) & SAMX5X_DID_SERIES_MASK;