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adiv5: Added handling for clearing memory tagging from the CSW value
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dragonmux committed Jul 29, 2023
1 parent 7abef6e commit fd55451
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Showing 2 changed files with 6 additions and 3 deletions.
2 changes: 1 addition & 1 deletion src/target/adiv5.c
Original file line number Diff line number Diff line change
Expand Up @@ -707,7 +707,7 @@ adiv5_access_port_s *adiv5_new_ap(adiv5_debug_port_s *dp, uint8_t apsel)
return NULL;
tmpap.csw = adiv5_ap_read(&tmpap, ADIV5_AP_CSW);
// XXX: We might be able to use the type field in ap->idr to determine if the AP supports TrustZone
tmpap.csw &= ~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK | ADIV5_AP_CSW_HNOSEC);
tmpap.csw &= ~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK | ADIV5_AP_CSW_MTE | ADIV5_AP_CSW_HNOSEC);
tmpap.csw |= ADIV5_AP_CSW_DBGSWENABLE;

if (tmpap.csw & ADIV5_AP_CSW_TRINPROG) {
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7 changes: 5 additions & 2 deletions src/target/adiv5.h
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@
#define ADIV5_SWD_TO_JTAG_SELECT_SEQUENCE 0xe73cU /* 16 bits, LSB (MSB: 0x3ce7) */
#define ADIV5_JTAG_TO_SWD_SELECT_SEQUENCE 0xe79eU /* 16 bits, LSB (MSB: 0x79e7) */

/*
/*
* ADIv5 Selection Alert sequence
* This sequence is sent MSB first and can be represented as either:
* - 0x49cf9046 a9b4a161 97f5bbc7 45703d98 transmitted MSB first
Expand Down Expand Up @@ -156,7 +156,10 @@
#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1U << 29U)
#define ADIV5_AP_CSW_HPROT1 (1U << 25U)
#define ADIV5_AP_CSW_SPIDEN (1U << 23U)
/* Bits 22:12 - Reserved */
/* Bits 22:16 - Reserved */
/* Bit 15 - MTE (Memory Tagging Enable) for AXI busses */
#define ADIV5_AP_CSW_MTE (1U << 15U)
/* Bits 14:12 - Reserved */
/* Bits 11:8 - Mode, must be zero */
#define ADIV5_AP_CSW_TRINPROG (1U << 7U)
#define ADIV5_AP_CSW_DEVICEEN (1U << 6U)
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