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swdptap: Handle no_delay parity/turnaround as well
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* This allows dropping the 0-loops check from delay_busy
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ALTracer committed Nov 25, 2023
1 parent 7df4414 commit f59f76f
Showing 1 changed file with 16 additions and 9 deletions.
25 changes: 16 additions & 9 deletions src/platforms/common/swdptap.c
Original file line number Diff line number Diff line change
Expand Up @@ -58,8 +58,6 @@ void swdptap_init(void)
static inline void platform_delay_busy(const uint32_t loops)
{
#if 1
if (loops < 1U)
return;
register uint32_t i = loops;
do {
__asm__("nop");
Expand All @@ -86,11 +84,13 @@ static void swdptap_turnaround(const swdio_status_t dir)
SWDIO_MODE_FLOAT();
} else {
gpio_clear(SWCLK_PORT, SWCLK_PIN);
platform_delay_busy(target_clk_divider + 1);
if (target_clk_divider != UINT32_MAX)
platform_delay_busy(target_clk_divider);
}

gpio_set(SWCLK_PORT, SWCLK_PIN);
platform_delay_busy(target_clk_divider + 1);
if (target_clk_divider != UINT32_MAX)
platform_delay_busy(target_clk_divider);

if (dir == SWDIO_STATUS_DRIVE) {
SWDIO_MODE_DRIVE();
Expand Down Expand Up @@ -141,13 +141,15 @@ static uint32_t swdptap_seq_in(size_t clock_cycles)
static bool swdptap_seq_in_parity(uint32_t *ret, size_t clock_cycles)
{
const uint32_t result = swdptap_seq_in(clock_cycles);
platform_delay_busy(target_clk_divider + 1);
if (target_clk_divider != UINT32_MAX)
platform_delay_busy(target_clk_divider);

size_t parity = __builtin_popcount(result);
parity += gpio_get(SWDIO_IN_PORT, SWDIO_IN_PIN) ? 1U : 0U;

gpio_set(SWCLK_PORT, SWCLK_PIN);
platform_delay_busy(target_clk_divider + 1);
if (target_clk_divider != UINT32_MAX)
platform_delay_busy(target_clk_divider);

*ret = result;
/* Terminate the read cycle now */
Expand Down Expand Up @@ -197,11 +199,16 @@ static void swdptap_seq_out(const uint32_t tms_states, const size_t clock_cycles

static void swdptap_seq_out_parity(const uint32_t tms_states, const size_t clock_cycles)
{
int parity = __builtin_popcount(tms_states);
const int parity = __builtin_popcount(tms_states);
swdptap_seq_out(tms_states, clock_cycles);

gpio_set_val(SWDIO_PORT, SWDIO_PIN, parity & 1U);
platform_delay_busy(target_clk_divider + 1);
if (target_clk_divider != UINT32_MAX)
platform_delay_busy(target_clk_divider);

gpio_set(SWCLK_PORT, SWCLK_PIN);
platform_delay_busy(target_clk_divider + 1);
if (target_clk_divider != UINT32_MAX)
platform_delay_busy(target_clk_divider);

gpio_clear(SWCLK_PORT, SWCLK_PIN);
}

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