Update Lab Material

assignment-06/README.md

@@ -18,9 +18,15 @@
 
 * Simulate 3 bits comparator in Xilinx ISim. You can use included testbench files.
 
+* Synthesis 3 Bit Comparator without any error and warning.
+
+* Save RTL Schematic of 3 bit comparator as a file.
+
 * Design 8 bits comparator using 3 bits comparator and write verilog code of it (***comparator8.v***).
 
-* complete  testbench file that design for validate the correctness of modules (***tb_comparator8.v***).
+* Complete testbench file of 8 bit comparator for validate the correctness of modules (***tb_comparator8.v***).
+
+* Synthesis 8 Bit comparator and report reason of any warning.
 
 ### Submission Sources
 * Source files (Grading Sources)

assignment-06/comparator3.v

@@ -23,16 +23,17 @@
 module comparator3 (
 	input [2:0] A ,
 	input [2:0] B ,
-	input 		l ,
-	input 		e ,
-	input 		g ,
-	output 		lt ,
-	output 		et ,
-	output 		gt
+	input l ,
+	input e ,
+	input g ,
+	output lt ,
+	output et ,
+	output gt
 );
 
 	/* write your code here */
 
 	/* write your code here */
 
 endmodule
+

assignment-06/comparator8.v

@@ -20,19 +20,20 @@
 -----------------------------------------------------------*/
 `timescale 1 ns/1 ns
 
-module comparator3 (
+module comparator8 (
 	input [7:0] A ,
 	input [7:0] B ,
-	input 		l ,
-	input 		e ,
-	input 		g ,
-	output 		lt ,
-	output 		et ,
-	output 		gt
+	input l ,
+	input e ,
+	input g ,
+	output lt ,
+	output et ,
+	output gt
 );
 
 	/* write your code here */
 
 	/* write your code here */
 
 endmodule
+

assignment-06/tb_comparator3.v

@@ -15,8 +15,8 @@
 --*/
 
 /*-----------------------------------------------------------
----  Module Name: Decoder Testbench
----  Description: Lab 05 Part 1 Testbench
+---  Module Name: 3 Bits Comparator Testbench
+---  Description: Lab 06 Part 1 Testbench
 -----------------------------------------------------------*/
 `timescale 1 ns/1 ns
 
@@ -39,53 +39,54 @@ wire gt;
 		begin
 
 		//////////////////
-		A <= 3'b001;
-		B <= 3'b001;
+		A = 3'b001;
+		B = 3'b001;
 
-		l <- 1'b0;
-		e <- 1'b1;
-		g <- 1'b0;
+		l = 1'b0;
+		e = 1'b1;
+		g = 1'b0;
 		# 10 ;
-		l <- 1'b1;
-		e <- 1'b0;
-		g <- 1'b0;
+		l = 1'b1;
+		e = 1'b0;
+		g = 1'b0;
 		# 10 ;
-		l <- 1'b0;
-		e <- 1'b0;
-		g <- 1'b1;
+		l = 1'b0;
+		e = 1'b0;
+		g = 1'b1;
 		# 20 ;
 		//////////////////
-		A <= 3'b010;
-		B <= 3'b001;
+		A = 3'b010;
+		B = 3'b001;
 
-		l <- 1'b0;
-		e <- 1'b1;
-		g <- 1'b0;
+		l = 1'b0;
+		e = 1'b1;
+		g = 1'b0;
 		# 10 ;
-		l <- 1'b1;
-		e <- 1'b0;
-		g <- 1'b0;
+		l = 1'b1;
+		e = 1'b0;
+		g = 1'b0;
 		# 10 ;
-		l <- 1'b0;
-		e <- 1'b0;
-		g <- 1'b1;
+		l = 1'b0;
+		e = 1'b0;
+		g = 1'b1;
 		# 20;
 		//////////////////
-		A <= 3'b001;
-		B <= 3'b010;
+		A = 3'b001;
+		B = 3'b010;
 
-		l <- 1'b0;
-		e <- 1'b1;
-		g <- 1'b0;
+		l = 1'b0;
+		e = 1'b1;
+		g = 1'b0;
 		# 10 ;
-		l <- 1'b1;
-		e <- 1'b0;
-		g <- 1'b0;
+		l = 1'b1;
+		e = 1'b0;
+		g = 1'b0;
 		# 10 ;
-		l <- 1'b0;
-		e <- 1'b0;
-		g <- 1'b1;
+		l = 1'b0;
+		e = 1'b0;
+		g = 1'b1;
 		# 20;
+		$finish;
 		//////////////////
 	end
 

assignment-06/tb_comparator8.v

@@ -15,24 +15,24 @@
 --*/
 
 /*-----------------------------------------------------------
----  Module Name: Decoder Testbench
----  Description: Lab 05 Part 1 Testbench
+---  Module Name: 8 Bit Comparator Testbench
+---  Description: Lab 06 Part 2 Testbench
 -----------------------------------------------------------*/
 `timescale 1 ns/1 ns
 
 
 module tb_comparator3 ();
 
-reg [2:0] A;
-reg [2:0] B;
+reg [7:0] A;
+reg [7:0] B;
 reg l;
 reg e;
 reg g;
 wire lt;
 wire et;
 wire gt;
 
-	comparator3 test_comparator3 (.A(A), .B(B), .l(l), .e(e), .g(g), .lt(lt), .et(et), .gt(gt));
+	comparator8 test_comparator8 (.A(A), .B(B), .l(l), .e(e), .g(g), .lt(lt), .et(et), .gt(gt));
 
 
 	initial