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Update HDL core version for Xilinx #155

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Sep 25, 2024
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2 changes: 1 addition & 1 deletion adijif/fpgas/xilinx.py
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ class xilinx(xilinx_bf):

max_serdes_lanes = 24

hdl_core_version = 1.0
hdl_core_version = 2.1

available_speed_grades = [-1, -2, -3]
speed_grade = -2
Expand Down
13 changes: 10 additions & 3 deletions tests/test_adrv9009.py
Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,15 @@ def test_adrv9009_rx_ad9528_solver_compact(solver):
sys.clock.d = [*range(1, 257)] # Limit output dividers

cfg = sys.solve()
print(cfg)
# print(cfg)
from pprint import pprint

pprint(cfg)

ref = {
"gekko": {"clock": {"r1": 2, "n2": 12, "m1": 5, "out_dividers": [6, 9, 192]}},
"gekko": {
"clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 32, 256]}
},
"CPLEX": {"clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 256]}},
}

Expand Down Expand Up @@ -89,7 +94,9 @@ def test_adrv9009_tx_ad9528_solver_compact(solver):
print(cfg)

ref = {
"gekko": {"clock": {"r1": 2, "n2": 12, "m1": 5, "out_dividers": [6, 9, 192]}},
"gekko": {
"clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 32, 256]}
},
"CPLEX": {"clock": {"r1": 2, "n2": 16, "m1": 4, "out_dividers": [1, 8, 256]}},
}

Expand Down
28 changes: 14 additions & 14 deletions tests/test_utils.py
Original file line number Diff line number Diff line change
Expand Up @@ -44,56 +44,56 @@ def test_generate_max_rates_fpga_utility():
"jesd_class": "jesd204b",
},
{
"sample_clock": 2500000000.0,
"bit_clock": 12500000000.0,
"sample_clock": 2062500000.0,
"bit_clock": 10312500000.0,
"L": 8,
"M": 2,
"quick_configuration_mode": "19.0",
"jesd_class": "jesd204b",
},
{
"sample_clock": 625000000.0,
"bit_clock": 12500000000.0,
"sample_clock": 515625000.0,
"bit_clock": 10312500000.0,
"L": 3,
"M": 3,
"quick_configuration_mode": "9.01",
"jesd_class": "jesd204b",
},
{
"sample_clock": 1250000000.0,
"bit_clock": 12500000000.0,
"sample_clock": 1031250000.0,
"bit_clock": 10312500000.0,
"L": 8,
"M": 4,
"quick_configuration_mode": "18.0",
"jesd_class": "jesd204b",
},
{
"sample_clock": 625000000.0,
"bit_clock": 12500000000.0,
"sample_clock": 515625000.0,
"bit_clock": 10312500000.0,
"L": 6,
"M": 6,
"quick_configuration_mode": "15.01",
"jesd_class": "jesd204b",
},
{
"sample_clock": 625000000.0,
"bit_clock": 12500000000.0,
"sample_clock": 515625000.0,
"bit_clock": 10312500000.0,
"L": 8,
"M": 8,
"quick_configuration_mode": "16.0",
"jesd_class": "jesd204b",
},
{
"sample_clock": 312500000.0,
"bit_clock": 12500000000.0,
"sample_clock": 257812500.0,
"bit_clock": 10312500000.0,
"L": 6,
"M": 12,
"quick_configuration_mode": "15.1",
"jesd_class": "jesd204b",
},
{
"sample_clock": 312500000.0,
"bit_clock": 12500000000.0,
"sample_clock": 257812500.0,
"bit_clock": 10312500000.0,
"L": 8,
"M": 16,
"quick_configuration_mode": "17.0",
Expand Down
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