docs: fpga_internal: fix minor typos and formatting

Signed-off-by: Liam Beguin <[email protected]>

docs/fpga_internal.md

@@ -4,7 +4,7 @@ JESD204 is a protocol that is made up of layers to manage the different aspects
 
 ![JESD204 Chain](imgs/jesd204_chain.png)
 
-From the diagram above, we can see in the FPGA there are explicit cores within the FPGA to manager the PHY Layer, Link Layer, and Transport Layer aspects for the JESD204 protocol. These will have specific drivers and HDL IP that need to configured for a configuration. By configuration, it primarily refers to the clocking and JESD modes. In the diagram there are both TX and RX data paths but generically they can considered identical, data will just flow in a specific direction in each case.
+From the diagram above, we can see in the FPGA there are explicit cores within the FPGA to manager the PHY Layer, Link Layer, and Transport Layer aspects for the JESD204 protocol. These will have specific drivers and HDL IP that need to configured for a configuration. By configuration, it primarily refers to the clocking and JESD modes. In the diagram there are both TX and RX data paths but generically they can be considered identical, data will just flow in a specific direction in each case.
 
 ## Clocking Layout
 
@@ -29,10 +29,10 @@ Technically, only the **device clock** is needed by the FPGA and all other clock
 ### Search Strategy
 
 There are two main unique cases when selecting the **ref clock** and **device clock**:
-* *N'* is not 8 or 16, or when *F* != 1, 2, or 4
-* Otherwise
+- *N'* is not 8 or 16, or when *F* != 1, 2, or 4
+- Otherwise
 
-In case (1) the **ref clock** is unlikely to be derived from the **device clock**. Therefore, two separate clocks need to be provided to the FPGA. Otherwise, only a single clock (ignoring **SYSREF**) is required. This is the general behavior based on current analysis; however, this is not a hard definition. The internal solver is configured to favor **ref clock** and **device clock** to be the same value. When this is not possible it will automatically create a secondary clock from the clock chip to be specifically used a the **device clock**. The generation of a separate clock for device clock can be forced by setting *force_separate_device_clock* in the *fpga* object instantiated in the *system* object.
+In case (1) the **ref clock** is unlikely to be derived from the **device clock**. Therefore, two separate clocks need to be provided to the FPGA. Otherwise, only a single clock (ignoring **SYSREF**) is required. This is the general behavior based on current analysis; however, this is not a hard definition. The internal solver is configured to favor **ref clock** and **device clock** to be the same value. When this is not possible it will automatically create a secondary clock from the clock chip to be specifically used as the **device clock**. The generation of a separate clock for device clock can be forced by setting *force_separate_device_clock* in the *fpga* object instantiated in the *system* object.
 
 ## API Controls