Fix formatting

Signed-off-by: Travis F. Collins <[email protected]>

adijif/clocks/ad9523_1_bf.py

@@ -34,7 +34,6 @@ def list_available_references(self, divider_set):
         ]
 
     def find_dividers(self, vcxo, required_output_rates, find=3):
-
         if self.use_vcxo_double:
             vcxo *= 2
 

adijif/clocks/ad9528_bf.py

@@ -35,7 +35,6 @@ def list_available_references(self, divider_set):
         ]
 
     def find_dividers(self, vcxo, required_output_rates, find=3):
-
         if self.use_vcxo_double:
             vcxo *= 2
 

adijif/clocks/hmc7044.py

@@ -452,7 +452,6 @@ def _get_clock_constraint(
             Exception: Invalid solver
         """
         if self.solver == "gekko":
-
             __d = self._d if isinstance(self._d, list) else [self._d]
 
             if __d.sort() != self.d_available.sort():
@@ -496,7 +495,6 @@ def set_requested_clocks(
 
         # Add requested clocks to output constraints
         for d_n, out_freq in enumerate(out_freqs):
-
             if self.solver == "gekko":
                 __d = self._d if isinstance(self._d, list) else [self._d]
                 if __d.sort() != self.d_available.sort():

adijif/clocks/hmc7044_bf.py

@@ -31,7 +31,6 @@ def list_available_references(self, divider_set):
         return [divider_set["vco"] / div for div in self.d_available]
 
     def find_dividers(self, vcxo, rates, find=3):
-
         if self.use_vcxo_double:
             vcxo *= 2
 

adijif/clocks/ltc6952.py

@@ -555,7 +555,6 @@ def _get_clock_constraint(
             Exception: Invalid solver
         """
         if self.solver == "gekko":
-
             __d = self._d if isinstance(self._d, list) else [self._d]
 
             if __d.sort() != self.d_available.sort():
@@ -594,7 +593,6 @@ def set_requested_clocks(
 
         # Add requested clocks to output constraints
         for out_freq in out_freqs:
-
             if self.solver == "gekko":
                 __d = self._d if isinstance(self._d, list) else [self._d]
                 if __d.sort() != self.d_available.sort():

adijif/clocks/ltc6952_bf.py

@@ -31,7 +31,6 @@ def list_available_references(self, divider_set):
         return [divider_set["vco"] / div for div in self.d_available]
 
     def find_dividers(self, vcxo, rates, find=3):
-
         v = []
         for mp in range(0, 32):
             for nx in range(0, 8):

adijif/clocks/ltc6953.py

@@ -425,7 +425,6 @@ def _setup_solver_constraints(self, input_ref: int) -> None:
         )
 
     def _setup(self, input_ref: int) -> None:
-
         if isinstance(input_ref, (float, int)):
             assert self.input_freq_max >= input_ref >= 0, "Input frequency out of range"
 
@@ -486,7 +485,6 @@ def set_requested_clocks(
 
         # Add requested clocks to output constraints
         for out_freq in out_freqs:
-
             if self.solver == "gekko":
                 __m = self._d if isinstance(self.__m, list) else [self.__m]
                 if __m.sort() != self.m_available.sort():

adijif/converters/ad9081.py

@@ -153,7 +153,6 @@ def _converter_clock_config(self) -> None:
         raise NotImplementedError
 
     def _pll_config(self, rxtx: bool = False) -> Dict:
-
         self._converter_clock_config()  # type: ignore
 
         self.config["ad9081_m_vco"] = self._convert_input([5, 7, 8, 11], "ad9081_m_vco")

adijif/converters/ad9144.py

@@ -185,7 +185,6 @@ def _check_valid_internal_configuration(self) -> None:
             assert self.K == 32, "K must be 32 for JESD mode 0, 4, or 9"
 
     def _pll_config(self) -> Dict:
-
         dac_clk = self.interpolation * self.sample_clock
         self.config["dac_clk"] = self._convert_input(dac_clk, "dac_clk")
 
@@ -195,7 +194,6 @@ def _pll_config(self) -> Dict:
         # a div of 32 would put you under supported range
 
         if self.solver == "gekko":
-
             self.config["ref_div_factor"] = self.model.sos1(
                 self.input_clock_divider_available
             )

adijif/fpgas/xilinx.py

@@ -434,7 +434,7 @@ def setup_by_dev_kit_name(self, name: str) -> None:
             raise Exception(f"No boardname found in library for {name}")
 
     def determine_pll(self, bit_clock: int, fpga_ref_clock: int) -> Dict:
-        """Determin if configuration is possible with CPLL or QPLL.
+        """Determine if configuration is possible with CPLL or QPLL.
 
         CPLL is checked first and will check QPLL if that case is
         invalid.
@@ -450,7 +450,7 @@ def determine_pll(self, bit_clock: int, fpga_ref_clock: int) -> Dict:
         """
         try:
             info = self.determine_cpll(bit_clock, fpga_ref_clock)
-        except BaseException:
+        except:  # noqa: B001
             info = self.determine_qpll(bit_clock, fpga_ref_clock)
         return info
 
@@ -1320,7 +1320,6 @@ def get_required_clocks(
             self.ref_clocks = []
             # obs = []
             for cnv in converter:  # type: ignore
-
                 # rsl = self._get_conv_prop(
                 #     cnv, self.requires_separate_link_layer_out_clock
                 # )

adijif/plls/adf4371.py

@@ -268,7 +268,6 @@ def _setup_solver_constraints(
 
         # Configure INT setting based on prescalers
         if self.solver == "CPLEX":
-
             self.config["frac1"] = integer_var(
                 min=self._frac1_min_max[0], max=self._frac1_min_max[1], name="frac1"
             )
@@ -370,7 +369,6 @@ def _setup_solver_constraints(
         )
 
     def _setup(self, input_ref: int) -> None:
-
         if isinstance(input_ref, (float, int)):
             assert (
                 self.input_freq_max >= input_ref >= self.input_freq_min

adijif/system.py

@@ -307,7 +307,6 @@ def solve(self) -> Dict:
         clock_names: List[str] = []
         config = {}
         if self.enable_converter_clocks:
-
             convs: List[convc] = (
                 self.converter if isinstance(self.converter, list) else [self.converter]
             )
@@ -319,7 +318,6 @@ def solve(self) -> Dict:
             sys_refs = []
 
             for conv in convs:
-
                 serdes_used += conv.L
                 if serdes_used > self.fpga.max_serdes_lanes:
                     raise Exception(
@@ -431,7 +429,6 @@ def solve(self) -> Dict:
                 # Setup fpga
                 if conv._nested:
                     for name in names:
-
                         if need_separate_link_clock:
                             self.fpga.get_required_clocks(
                                 getattr(conv, name),

tests/test_adf4371.py

@@ -7,7 +7,6 @@
 
 
 def test_adf4371_datasheet_example():
-
     pll = adijif.adf4371()
     pll._MOD2 = 1536
     pll.rf_div = 2
@@ -43,7 +42,6 @@ def test_adf4371_datasheet_example():
 
 
 def test_adf4371_ad9081_sys_example():
-
     vcxo = 100e6
 
     sys = adijif.system("ad9081", "hmc7044", "xilinx", vcxo, solver="CPLEX")
@@ -104,7 +102,6 @@ def test_adf4371_ad9081_sys_example():
     ["4/5", "8/9", ["4/5", "8/9"]],
 )
 def test_adf4371_vary_modes(mode, int_prescaler):
-
     pll = adijif.adf4371()
     pll.mode = mode
     pll._prescaler = int_prescaler
@@ -140,7 +137,6 @@ def test_adf4371_vary_modes(mode, int_prescaler):
 
 
 def test_adf4371_touch_all_properties():
-
     pll = adijif.adf4371()
 
     # read/write all

tests/test_bf.py

@@ -464,7 +464,6 @@ def test_ad9523_1_daq2_config_force_m2():
 
 
 def test_daq2_fpga_qpll_rxtx_zc706_config():
-
     # Full bandwidth example 1b
     clk = adijif.ad9523_1()
     rates = 1e9

tests/test_clocks.py

@@ -9,7 +9,6 @@
 
 @pytest.mark.parametrize("solver", ["gekko", "CPLEX"])
 def test_ad9545_validate_fail(solver):
-
     msg = r"Solution Not Found"
 
     with pytest.raises(Exception, match=msg):
@@ -32,7 +31,6 @@ def test_ad9545_validate_fail(solver):
 @pytest.mark.parametrize("solver", ["gekko", "CPLEX"])
 @pytest.mark.parametrize("out_freq", [30720000, 25e6])
 def test_ad9545_validate_pass(solver, out_freq):
-
     clk = adijif.ad9545(solver=solver)
 
     clk.avoid_min_max_PLL_rates = True
@@ -77,7 +75,6 @@ def test_ad9545_validate_pass(solver, out_freq):
 
 
 def test_ad9545_fail_no_solver():
-
     with pytest.raises(Exception, match=r"Unknown solver NAN"):
         clk = adijif.ad9545(solver="NAN")
 
@@ -93,7 +90,6 @@ def test_ad9545_fail_no_solver():
 
 
 def test_ad9523_1_daq2_validate():
-
     vcxo = 125000000
     n2 = 24
 
@@ -124,7 +120,6 @@ def test_ad9523_1_daq2_validate():
 
 
 def test_ad9523_1_daq2_cplex_validate():
-
     vcxo = 125000000
     n2 = 24
 
@@ -161,7 +156,6 @@ def test_ad9523_1_daq2_cplex_validate():
 
 @pytest.mark.parametrize("solver", ["geko", "CPLEX"])
 def test_ad9523_1_daq2_validate_fail(solver):
-
     msg = r"Solution Not Found"
 
     with pytest.raises(Exception, match=msg):
@@ -194,7 +188,6 @@ def test_ad9523_1_daq2_validate_fail(solver):
 
 
 def test_ad9523_1_daq2_validate_fail_cplex():
-
     with pytest.raises(Exception, match=r"Solution Not Found"):
         vcxo = 125000000
         n2 = 12
@@ -224,7 +217,6 @@ def test_ad9523_1_daq2_validate_fail_cplex():
 
 @pytest.mark.parametrize("solver", ["gekko", "CPLEX"])
 def test_ad9523_1_daq2_variable_vcxo_validate(solver):
-
     vcxo = adijif.types.range(100000000, 126000000, 1000000, "vcxo")
     n2 = 24
 
@@ -257,7 +249,6 @@ def test_ad9523_1_daq2_variable_vcxo_validate(solver):
 
 
 def test_ad9523_1_fail_no_solver():
-
     with pytest.raises(Exception, match=r"Unknown solver NAN"):
         clk = adijif.ad9523_1(solver="NAN")
         output_clocks = [1e9, 500e6, 7.8125e6]
@@ -267,7 +258,6 @@ def test_ad9523_1_fail_no_solver():
 
 
 def test_ad9523_1_fail_no_solver2():
-
     with pytest.raises(Exception, match=r"Unknown solver NAN2"):
         vcxo = 125000000
         clk = adijif.ad9523_1()
@@ -279,7 +269,6 @@ def test_ad9523_1_fail_no_solver2():
 
 
 def test_ad9523_1_fail_no_solver3():
-
     with pytest.raises(Exception, match=r"Unknown solver NAN3"):
         vcxo = 125000000
         clk = adijif.ad9523_1()
@@ -291,15 +280,13 @@ def test_ad9523_1_fail_no_solver3():
 
 
 def test_system_fail_no_solver3():
-
     with pytest.raises(Exception, match=r"Unknown solver NAN4"):
         vcxo = 125000000
         sys = adijif.system("ad9680", "hmc7044", "xilinx", vcxo, solver="NAN4")
         sys.solve()
 
 
 def test_ltc6953_validate():
-
     ref_in = adijif.types.range(1000000000, 4500000000, 1000000, "ref_in")
 
     clk = adijif.ltc6953(solver="CPLEX")

tests/test_daq2.py

@@ -11,7 +11,6 @@
 
 @pytest.mark.parametrize("solver", solvers_to_test)
 def test_smoke_solver(solver):
-
     vcxo = 125000000
     sys = adijif.system("ad9680", "hmc7044", "xilinx", vcxo, solver=solver)
     sys.fpga.setup_by_dev_kit_name("zc706")
@@ -34,7 +33,6 @@ def test_smoke_solver(solver):
 @pytest.mark.parametrize("clockchip", ["ad9528", "hmc7044", "ad9523_1"])
 @pytest.mark.parametrize("fpga_kit", ["zc706", "zcu102"])
 def test_smoke_all_clocks(solver, converter, clockchip, fpga_kit):
-
     vcxo = 125000000
     sys = adijif.system(converter, clockchip, "xilinx", vcxo, solver=solver)
     sys.fpga.setup_by_dev_kit_name(fpga_kit)
@@ -76,7 +74,6 @@ def test_smoke_all_clocks(solver, converter, clockchip, fpga_kit):
 def test_ad9680_all_clk_chips_fpga_pll_modes_solver(
     qpll, cpll, rate, clock_chip, solver, fpga_kit
 ):
-
     if fpga_kit == "zcu102" and clock_chip == "hmc7044" and rate == 1e9:
         pytest.skip()
 
@@ -123,7 +120,6 @@ def test_ad9680_all_clk_chips_fpga_pll_modes_solver(
 
 @pytest.mark.parametrize("solver", solvers_to_test)
 def test_daq2_split_rates_solver(solver):
-
     vcxo = 125000000
     sys = adijif.system(["ad9680", "ad9144"], "ad9523_1", "xilinx", vcxo, solver=solver)
     sys.fpga.setup_by_dev_kit_name("zc706")
@@ -158,7 +154,6 @@ def test_daq2_split_rates_solver(solver):
 
 
 def test_ad9680_clock_check1_solver():
-
     vcxo = 125000000
     sys = adijif.system("ad9680", "ad9523_1", "xilinx", vcxo)
 
@@ -181,7 +176,6 @@ def test_ad9680_clock_check1_solver():
 @pytest.mark.xfail(reason="Need to verify settings")
 @pytest.mark.parametrize("solver", solvers_to_test)
 def test_ad9680_clock_check2_solver(solver):
-
     vcxo = 125000000
 
     sys = adijif.system("ad9680", "ad9523_1", "xilinx", vcxo, solver=solver)