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Update drawing to work at system level and indepently on components
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Signed-off-by: Travis F. Collins <[email protected]>
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tfcollins committed Jun 18, 2024
1 parent d2f6bb1 commit 458c014
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Showing 6 changed files with 274 additions and 116 deletions.
12 changes: 10 additions & 2 deletions adijif/converters/ad9680.py
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,15 @@ def _convert_to_config(
CS: Union[int, float],
) -> Dict:
# return {"L": L, "M": M, "F": F, "S": S, "HD": HD, "N": N, "Np": Np, "CS": CS}
return {"L": L, "M": M, "F": F, "S": S, "HD": HD, "Np": Np, "jesd_class": "jesd204b"}
return {
"L": L,
"M": M,
"F": F,
"S": S,
"HD": HD,
"Np": Np,
"jesd_class": "jesd204b",
}


quick_configuration_modes = {
Expand Down Expand Up @@ -154,7 +162,7 @@ def get_required_clock_names(self) -> List[str]:
Returns:
List[str]: List of strings of clock names in order
"""
return ["ad9680_adc_clock", "ad9680_sysref"]
return ["AD9680_ref_clk", "AD9680_sysref"]

def get_required_clocks(self) -> List:
"""Generate list required clocks.
Expand Down
27 changes: 17 additions & 10 deletions adijif/converters/ad9680_draw.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@

from adijif.draw import Layout, Node # type: ignore # isort: skip # noqa: I202


class ad9680_draw:

_system_draw = False
Expand All @@ -12,7 +13,6 @@ def _init_diagram(self) -> None:
self.ic_diagram_node = None
self._diagram_output_dividers = []


self.ic_diagram_node = Node("AD9680")

# External
Expand All @@ -39,7 +39,6 @@ def _init_diagram(self) -> None:
ddc = self.ic_diagram_node.get_child(f"DDC{ddc}")
self.ic_diagram_node.add_connection({"from": ddc, "to": jesd204_framer})


def _update_diagram(self, config: Dict) -> None:
"""Update diagram with configuration.
Expand Down Expand Up @@ -78,7 +77,7 @@ def draw(self, clocks, lo=None, clock_chip_node=None) -> str:
"""
if not self._saved_solution:
raise Exception("No solution to draw. Must call solve first.")

system_draw = lo is not None

if not system_draw:
Expand All @@ -92,6 +91,7 @@ def draw(self, clocks, lo=None, clock_chip_node=None) -> str:

if not system_draw:
ref_in = Node("REF_IN", ntype="input")
lo.add_node(ref_in)
else:
to_node = lo.get_node("AD9680_ref_clk")
# Locate node connected to this one
Expand All @@ -103,19 +103,20 @@ def draw(self, clocks, lo=None, clock_chip_node=None) -> str:
# Remove to_node since it is not needed
lo.remove_node(to_node.name)

lo.add_node(ref_in)
for i in range(2):
adc = self.ic_diagram_node.get_child(f"ADC{i}")
lo.add_connection({"from": ref_in, "to": adc, "rate": clocks["AD9680_ref_clk"]})
lo.add_connection(
{"from": ref_in, "to": adc, "rate": clocks["AD9680_ref_clk"]}
)

# Update Node values
for ddc in range(4):
rate = clocks["AD9680_ref_clk"]
rate = clocks["AD9680_ref_clk"]
self.ic_diagram_node.update_connection("Crossbar", f"DDC{ddc}", rate)

ddc_node = self.ic_diagram_node.get_child(f"DDC{ddc}")
ddc_node.value = str(static_options["decimation"])
drate = rate/static_options["decimation"]
drate = rate / static_options["decimation"]

self.ic_diagram_node.update_connection(f"DDC{ddc}", "JESD204 Framer", drate)

Expand Down Expand Up @@ -155,7 +156,13 @@ def draw(self, clocks, lo=None, clock_chip_node=None) -> str:
# Add connect for each lane
for i in range(self.L):
lane_rate = self.bit_clock
lo.add_connection({"from": self.ic_diagram_node.get_child("JESD204 Framer"), "to": remote_deframer, "rate": lane_rate})
lo.add_connection(
{
"from": self.ic_diagram_node.get_child("JESD204 Framer"),
"to": remote_deframer,
"rate": lane_rate,
}
)

if not system_draw:
return lo.draw()
return lo.draw()
8 changes: 4 additions & 4 deletions adijif/draw.py
Original file line number Diff line number Diff line change
Expand Up @@ -135,7 +135,7 @@ def get_child(self, name: str) -> Node:
if child.name == name:
return child
raise ValueError(f"Child with name {name} not found.")

def remove_child(self, name: str) -> None:
"""Remove child node by name.
Expand Down Expand Up @@ -262,7 +262,6 @@ def get_connection(self, from_s: str = None, to: str = None) -> dict:
if conn["from"].name == from_s and conn["to"].name == to:
return conn


def get_node(self, name: str) -> Node:
"""Get node by name.
Expand Down Expand Up @@ -370,9 +369,9 @@ def draw_nodes_connections(nodes):

if node.children:
diag += draw_nodes_connections(node.children)

return diag

# for node in self.nodes:
diag += draw_nodes_connections(self.nodes)

Expand Down Expand Up @@ -402,6 +401,7 @@ def draw_nodes_connections(nodes):

# Use bindings
from .d2 import compile

out = compile(diag)
# with open(self.output_image_filename, "w") as f:
# f.write(out)
Expand Down
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