Update SERDES lane counting to handle JTX and JRX separately

Signed-off-by: Travis F. Collins <[email protected]>

adijif/converters/ad9081.py

@@ -284,6 +284,7 @@ class ad9081_rx(adc, ad9081_core):
     """AD9081 Receive model."""
 
     name = "AD9081_RX"
+    converter_type = "adc"
 
     converter_clock_min = 1.45e9
     converter_clock_max = 4e9
@@ -393,6 +394,7 @@ class ad9081_tx(dac, ad9081_core):
     """AD9081 Transmit model."""
 
     name = "AD9081_TX"
+    converter_type = "dac"
 
     converter_clock_min = 2.9e9
     converter_clock_max = 12e9
@@ -480,6 +482,7 @@ class ad9081(ad9081_core):
     converter_clock_max = ad9081_rx.converter_clock_max
     quick_configuration_modes: Dict[str, Any] = {}
     _nested = ["adc", "dac"]
+    converter_type = "adc_dac"
 
     def __init__(
         self, model: Union[GEKKO, CpoModel] = None, solver: str = None

adijif/converters/ad9144.py

@@ -80,6 +80,7 @@ class ad9144(ad9144_bf):
     """
 
     name = "AD9144"
+    converter_type = "DAC"
 
     # JESD parameters
     _jesd_params_to_skip_check = ["DualLink", "K"]

adijif/converters/ad9680.py

@@ -55,6 +55,7 @@ class ad9680(ad9680_bf):
     """
 
     name = "AD9680"
+    converter_type = "adc"
 
     # JESD parameters
     _jesd_params_to_skip_check = ["DualLink", "CS", "N", "HD"]

adijif/converters/adrv9009.py

@@ -189,6 +189,7 @@ class adrv9009_rx(adc, adrv9009_clock_common, adrv9009_core):
 
     quick_configuration_modes = {"jesd204b": quick_configuration_modes_rx}
     name = "ADRV9009_RX"
+    converter_type = "adc"
 
     # JESD configurations
     K_available = [*np.arange(1, 32 + 1)]
@@ -232,6 +233,7 @@ class adrv9009_tx(dac, adrv9009_clock_common, adrv9009_core):
 
     quick_configuration_modes = {"jesd204b": quick_configuration_modes_tx}
     name = "ADRV9009_TX"
+    converter_type = "dac"
 
     # JESD configurations
     K_available = [*np.arange(1, 32 + 1)]
@@ -269,6 +271,7 @@ class adrv9009(adrv9009_core):
     name = "ADRV9009"
     solver = "CPLEX"
     _nested = ["adc", "dac"]
+    converter_type = "adc_dac"
 
     def __init__(
         self, model: Union[GEKKO, CpoModel] = None, solver: str = None

adijif/converters/converter.py

@@ -119,6 +119,16 @@ def get_current_jesd_mode_settings(self) -> Dict:
             current_config[attr] = getattr(self, attr)
         return current_config
 
+    @property
+    @abstractmethod
+    def converter_type(self) -> str:
+        """Type of converter. ADC or DAC.
+
+        Returns:
+            str: Type of converter
+        """
+        raise NotImplementedError
+
     @property
     @abstractmethod
     def clocking_option_available(self) -> List[str]:

adijif/system.py

@@ -314,18 +314,33 @@ def solve(self) -> Dict:
             # Setup clock chip
             self.clock._setup(self.vcxo)
             self.fpga.configs = []  # reset
-            serdes_used: float = 0
+            serdes_used_tx: int = 0
+            serdes_used_rx: int = 0
             sys_refs = []
 
             for conv in convs:
-                # MIX ME, this need to be directional!!!
-                # if conv._nested:  # MxFE, Transceivers
-                #     for name in conv._nested:
-                #         serdes_used += getattr(conv, name).L
-                # else:
-                #     serdes_used += conv.L
-
-                if serdes_used > self.fpga.max_serdes_lanes:
+                if conv._nested:  # MxFE, Transceivers
+                    for name in conv._nested:
+                        ctype = getattr(conv, name).converter_type.lower()
+                        if ctype == "adc":
+                            serdes_used_rx += getattr(conv, name).L
+                        elif ctype == "dac":
+                            serdes_used_tx += getattr(conv, name).L
+                        else:
+                            raise Exception(f"Unknown converter type {ctype}")
+                else:
+                    ctype = conv.converter_type.lower()
+                    if ctype == "adc":
+                        serdes_used_rx += conv.L
+                    elif ctype == "dac":
+                        serdes_used_tx += conv.L
+                    else:
+                        raise Exception(f"Unknown converter type: {ctype}")
+
+                if (
+                    serdes_used_rx > self.fpga.max_serdes_lanes
+                    or serdes_used_tx > self.fpga.max_serdes_lanes
+                ):
                     raise Exception(
                         "Max SERDES lanes exceeded. {} only available".format(
                             self.fpga.max_serdes_lanes

tests/test_system.py

@@ -64,7 +64,7 @@ def test_nested_converter_lane_count_valid():
 
 
 def test_nested_converter_lane_count_exceeds_fpga_lane_count():
-    fpga_L = 2
+    fpga_L = 1
 
     sys = adijif.system("adrv9009", "ad9528", "xilinx", 122.88e6)