Analysis of performance of approximate arithmetic circuits compared to their precise counterparts.
In this project I have implemented a 32-bit, RISC-V ISA based processor in verilog with a low latency approximate adder and analysed its performance relative to an accurate adder. I have made two separate models of the processor in verilog. One of them uses a low latency approximate adder instead of a normal adder. As a result it produces some error. Such non-precise adders can be used for certain applications where we can safely tradeoff accuracy for reducing area and power usage. The sub-modules that are used and their interaction with each other are shown in the following picture.
Each sqaure represents difference of the results obtained by the exact and approximate processor models when both the models add the same two numbers. The intensity of the colour signifies magnitude of the error.
