directories.txt

├── project_directory/
│   ├── iscas_benchmarks/          # ISCAS benchmark Verilog files directory
│   │   ├── c17.v                  # ISCAS benchmark Verilog file (e.g., c17, s27, etc.)
│   │   ├── s27.v
│   │
│   ├── scripts/                   # Scripts directory
│   │   ├── generate_json.ys       # Yosys script to generate JSON (modified for ISCAS)
│   │   ├── extract_outputs.py     # Python script to extract outputs from JSON
│   │   ├── run_cones.sh           # Bash script to automate the process for ISCAS benchmarks
│   │
│   ├── logic_cones/               # Directory for Yosys-generated BLIF files
│   ├── optimized_cones/           # Directory for ABC-optimized BLIF files
│   ├── tlg_conversion.py          # Python script for TLG conversion
│   ├── design.json                # JSON file generated by Yosys
│   └── output_logs/               # Optional: directory for logs (if needed)