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[MachineSink] Check predecessor/successor relationship between two ba…
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…sic blocks involved in critical edge splitting (llvm#98540)

Fix an issue in llvm#97618 - if the two basic blocks involved are not
predecessor / successor to each other, treat the candidate as illegal
for critical edge splitting.

Closes llvm#98477 (checked in test copied from its comment).
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yozhu authored and aaryanshukla committed Jul 16, 2024
1 parent b2346aa commit 982f284
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineSink.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -961,7 +961,7 @@ bool MachineSinking::isLegalToBreakCriticalEdge(MachineInstr &MI,
MachineBasicBlock *ToBB,
bool BreakPHIEdge) {
// Avoid breaking back edge. From == To means backedge for single BB cycle.
if (!SplitEdges || FromBB == ToBB)
if (!SplitEdges || FromBB == ToBB || !FromBB->isSuccessor(ToBB))
return false;

MachineCycle *FromCycle = CI->getCycle(FromBB);
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76 changes: 76 additions & 0 deletions llvm/test/CodeGen/X86/MachineSink-Issue98477.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s | FileCheck %s

target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define i32 @main(i1 %tobool.not, i32 %0) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $1, %r8d
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB0_8
; CHECK-NEXT: .LBB0_1: # %j.preheader
; CHECK-NEXT: xorl %r9d, %r9d
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_5: # %if.then4
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %r8d
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB0_6
; CHECK-NEXT: .LBB0_2: # %j
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: idivl %esi
; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: testb %r9b, %r9b
; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: # %bb.3: # %j
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: testl %r9d, %r9d
; CHECK-NEXT: js .LBB0_5
; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: movl %r9d, %edx
; CHECK-NEXT: .LBB0_6: # %if.end9
; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: jne .LBB0_7
; CHECK-NEXT: .LBB0_8: # %if.end13
; CHECK-NEXT: xorl %r8d, %r8d
; CHECK-NEXT: jmp .LBB0_1
; CHECK-NEXT: .LBB0_7: # %while.body.lr.ph
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retq
entry:
br i1 %tobool.not, label %if.end13, label %j.preheader

j.preheader: ; preds = %if.end13, %entry
%h.0.ph = phi i32 [ 1, %entry ], [ 0, %if.end13 ]
br label %j

j: ; preds = %if.then4, %j.preheader
%1 = phi i32 [ %div2, %if.then4 ], [ 0, %j.preheader ]
%rem1 = srem i32 1, %0
%cmp = icmp slt i32 %1, 0
%or.cond = select i1 false, i1 true, i1 %cmp
br i1 %or.cond, label %if.then4, label %if.end9

if.then4: ; preds = %j
%div2 = sdiv i32 1, 0
%rem5 = srem i32 1, %h.0.ph
br i1 %tobool.not, label %if.end9, label %j

if.end9: ; preds = %if.then4, %j
%2 = phi i32 [ 0, %j ], [ %rem5, %if.then4 ]
%tobool10.not = icmp eq i32 %2, 0
br i1 %tobool10.not, label %if.end13, label %while.body.lr.ph

while.body.lr.ph: ; preds = %if.end9
ret i32 %rem1

if.end13: ; preds = %if.end9, %entry
br label %j.preheader
}

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