Skip to content

Commit

Permalink
Build: (9a7b6c6) Update versal_acap_cpm_example_designs.rst
Browse files Browse the repository at this point in the history
  • Loading branch information
@deepesh2017
deepesh2017 committed Nov 18, 2023
1 parent c1401a0 commit 6a890c0
Show file tree
Hide file tree
Showing 6 changed files with 69 additions and 25 deletions.
Binary file modified ...octrees/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.doctree
View file
Binary file not shown.
Binary file modified pciedebug/build/doctrees/environment.pickle
View file
Binary file not shown.
24 changes: 16 additions & 8 deletions ...cs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,19 +4,27 @@ Versal ACAP CPM Example Designs
===============================

* Versal ACAP CPM5 QDMA Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_QDMA_Simulation_Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma
* Versal ACAP CPM4 QDMA Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma
* Veral ACAP CPM5 BMD Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_PCIe_BMD_Simulation_Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd
* Veral ACAP CPM4 BMD Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd
* Versal ACAP CPM - Using PCIe Link for Debug
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug
* Veral ACAP Tandem PCIe Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe
* Versal ACAP CPM AXI Bridge Root Complex Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_AXI_Bridge_RootPort_Design
* Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design
* Versal ACAP CPM Gen4x8 QDMA Endpoint Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_Gen4x8_QDMA_EP_Design
* Versal ACAP CPM PCIE PIO Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_PCIE_PIO_Design
* Versal ACAP CPM PCIE BMD Example Design for VCK190
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/VCK190_CPM_PCIE_BMD
* Versal ACAP CPM5 PCIE PIO Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio
* Versal ACAP CPM4 PCIE PIO Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio
* Versal ACAP CPM5 PCIE BMD EndPoint Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep
* Versal ACAP CPM4 PCIE BMD EndPoint Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep

44 changes: 36 additions & 8 deletions ...build/html/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -130,14 +130,28 @@
<ul class="simple">
<li><dl class="simple">
<dt>Versal ACAP CPM5 QDMA Simulation Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_QDMA_Simulation_Design">https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_QDMA_Simulation_Design</a></p></li>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma</a></p></li>
</ul>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Versal ACAP CPM4 QDMA Simulation Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma</a></p></li>
</ul>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Veral ACAP CPM5 BMD Simulation Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_PCIe_BMD_Simulation_Design">https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_PCIe_BMD_Simulation_Design</a></p></li>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd</a></p></li>
</ul>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Veral ACAP CPM4 BMD Simulation Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd</a></p></li>
</ul>
</dd>
</dl>
Expand All @@ -157,8 +171,8 @@
</dl>
</li>
<li><dl class="simple">
<dt>Versal ACAP CPM AXI Bridge Root Complex Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_AXI_Bridge_RootPort_Design">https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_AXI_Bridge_RootPort_Design</a></p></li>
<dt>Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design</a></p></li>
</ul>
</dd>
</dl>
Expand All @@ -171,15 +185,29 @@
</dl>
</li>
<li><dl class="simple">
<dt>Versal ACAP CPM PCIE PIO Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_PCIE_PIO_Design">https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_PCIE_PIO_Design</a></p></li>
<dt>Versal ACAP CPM5 PCIE PIO Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio</a></p></li>
</ul>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Versal ACAP CPM4 PCIE PIO Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio</a></p></li>
</ul>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Versal ACAP CPM5 PCIE BMD EndPoint Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep</a></p></li>
</ul>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Versal ACAP CPM PCIE BMD Example Design for VCK190</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/VCK190_CPM_PCIE_BMD">https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/VCK190_CPM_PCIE_BMD</a></p></li>
<dt>Versal ACAP CPM4 PCIE BMD EndPoint Example Design</dt><dd><ul>
<li><p><a class="reference external" href="https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep">https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep</a></p></li>
</ul>
</dd>
</dl>
Expand Down
2 changes: 1 addition & 1 deletion pciedebug/build/html/searchindex.js
View file

Large diffs are not rendered by default.

24 changes: 16 additions & 8 deletions ...e/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,19 +4,27 @@ Versal ACAP CPM Example Designs
===============================

* Versal ACAP CPM5 QDMA Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_QDMA_Simulation_Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma
* Versal ACAP CPM4 QDMA Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma
* Veral ACAP CPM5 BMD Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_PCIe_BMD_Simulation_Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd
* Veral ACAP CPM4 BMD Simulation Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd
* Versal ACAP CPM - Using PCIe Link for Debug
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug
* Veral ACAP Tandem PCIe Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe
* Versal ACAP CPM AXI Bridge Root Complex Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_AXI_Bridge_RootPort_Design
* Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design
* Versal ACAP CPM Gen4x8 QDMA Endpoint Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_Gen4x8_QDMA_EP_Design
* Versal ACAP CPM PCIE PIO Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_PCIE_PIO_Design
* Versal ACAP CPM PCIE BMD Example Design for VCK190
- https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/VCK190_CPM_PCIE_BMD
* Versal ACAP CPM5 PCIE PIO Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio
* Versal ACAP CPM4 PCIE PIO Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio
* Versal ACAP CPM5 PCIE BMD EndPoint Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep
* Versal ACAP CPM4 PCIE BMD EndPoint Example Design
- https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep

0 comments on commit 6a890c0

Please sign in to comment.