Update tables.rst

Xilinx · Sep 22, 2024 · 4c1c8cf · 4c1c8cf
1 parent 04eaeef
commit 4c1c8cf
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/...e/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst b/...e/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst
@@ -18,7 +18,10 @@ AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions
 
 .. note::
 
-   See the latest version of PG302 for updates
+   The table above is sourced from PG302. Refer to the links below for the relevant IP table.
+   PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Global-Ports
+   PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?tocId=OZuHNoSk7b_ljTFaCFeXow
+   PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Global-Ports
 
 .. _axi4_memory_mapped_master_bridge_read_interface_port_descriptions: