Build: (4c1c8cf) Update tables.rst

Xilinx · Sep 22, 2024 · 4ba60a3 · 4ba60a3
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Showing 6 changed files with 13 additions and 4 deletions.
diff --git a/...octrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.doctree b/...octrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.doctree
diff --git a/pciedebug/build/doctrees/environment.pickle b/pciedebug/build/doctrees/environment.pickle
diff --git a/...cs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst.txt b/...cs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst.txt
@@ -18,7 +18,10 @@ AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions
 
 .. note::
 
-   See the latest version of PG302 for updates
+   The table above is sourced from PG302. Refer to the links below for the relevant IP table.
+   PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Global-Ports
+   PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?tocId=OZuHNoSk7b_ljTFaCFeXow
+   PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Global-Ports
 
 .. _axi4_memory_mapped_master_bridge_read_interface_port_descriptions:
 

diff --git a/...build/html/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.html b/...build/html/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.html
@@ -131,7 +131,10 @@
 <img alt="../../../../_images/002_axi4_memory_mapped_master_bridge_read_address_interface_port_descriptions.png" class="align-center" src="../../../../_images/002_axi4_memory_mapped_master_bridge_read_address_interface_port_descriptions.png" />
 <div class="admonition note">
 <p class="admonition-title">Note</p>
-<p>See the latest version of PG302 for updates</p>
+<p>The table above is sourced from PG302. Refer to the links below for the relevant IP table.
+PG302: <a class="reference external" href="https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Global-Ports">https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Global-Ports</a>
+PG344: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?tocId=OZuHNoSk7b_ljTFaCFeXow">https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?tocId=OZuHNoSk7b_ljTFaCFeXow</a>
+PG347: <a class="reference external" href="https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Global-Ports">https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Global-Ports</a></p>
 </div>
 </div>
 <div class="section" id="axi4-memory-mapped-master-bridge-read-interface-port-descriptions">

diff --git a/pciedebug/build/html/searchindex.js b/pciedebug/build/html/searchindex.js
diff --git a/...e/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst b/...e/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst
@@ -18,7 +18,10 @@ AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions
 
 .. note::
 
-   See the latest version of PG302 for updates
+   The table above is sourced from PG302. Refer to the links below for the relevant IP table.
+   PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Global-Ports
+   PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?tocId=OZuHNoSk7b_ljTFaCFeXow
+   PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Global-Ports
 
 .. _axi4_memory_mapped_master_bridge_read_interface_port_descriptions: