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Compile test_utils at build time, use it in more tests (#1783)
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fifield authored Sep 23, 2024
1 parent 51184e5 commit d630495
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Showing 151 changed files with 307 additions and 1,077 deletions.
1 change: 1 addition & 0 deletions runtime_lib/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -111,6 +111,7 @@ foreach(target ${AIE_RUNTIME_TARGETS})
-DLibXAIE_INC_DIR=${XILINX_XAIE_INCLUDE_DIR}
-DVITIS_ROOT=${VITIS_ROOT}
-DVITIS_AIETOOLS_DIR=${VITIS_AIETOOLS_DIR}
-DXRT_ROOT=${XRT_ROOT}
-DSysroot=${Sysroot}
-Dhsa-runtime64_DIR=${hsa-runtime64_DIR}
-Dhsakmt_DIR=${hsakmt_DIR}
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39 changes: 34 additions & 5 deletions runtime_lib/test_lib/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ cmake_minimum_required(VERSION 3.21)

project("test lib for ${AIE_RUNTIME_TARGET}")

# test_lib library
add_library(test_lib STATIC test_library.cpp)
set(TEST_LIB_PUBLIC_HEADERS
test_library.h
Expand Down Expand Up @@ -40,8 +41,23 @@ if (${AIE_RUNTIME_TARGET} STREQUAL "x86_64-hsa")

endif()

# copy header and source files into build area
set(headers target.h test_library.h memory_allocator.h hsa_ext_air.h)
find_package(XRT)
set(BUILD_TEST_UTILS ${XRT_FOUND} AND NOT ${AIE_RUNTIME_TARGET} STREQUAL "x86_64-hsa")

# test_utils library
if (${BUILD_TEST_UTILS})
add_library(test_utils STATIC test_utils.cpp)
set_target_properties(test_utils PROPERTIES PUBLIC_HEADER test_utils.h)
target_compile_options(test_utils PRIVATE -fPIC)

target_include_directories(test_utils PRIVATE
${LibXAIE_INC_DIR}
${XRT_INCLUDE_DIR}
)
endif()

# copy test_library and test_utils header files into build area
set(headers target.h test_library.h test_utils.h memory_allocator.h hsa_ext_air.h)
foreach(basefile ${headers})
set(dest ${CMAKE_CURRENT_BINARY_DIR}/../include/${basefile})
add_custom_target(aie-copy-runtime-libs-${basefile} ALL DEPENDS ${dest})
Expand All @@ -51,7 +67,8 @@ foreach(basefile ${headers})
)
endforeach()

set(files test_library.cpp)
# copy test_library and test_utils source files into build area
set(files test_library.cpp test_utils.cpp)
foreach(basefile ${files})
set(dest ${CMAKE_CURRENT_BINARY_DIR}/../src/${basefile})
add_custom_target(aie-copy-runtime-libs-${basefile} ALL DEPENDS ${dest})
Expand All @@ -65,10 +82,21 @@ install(TARGETS test_lib
ARCHIVE DESTINATION ${CMAKE_INSTALL_PREFIX}/runtime_lib/${AIE_RUNTIME_TARGET}/test_lib/lib
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_PREFIX}/runtime_lib/${AIE_RUNTIME_TARGET}/test_lib/include
)
if (${BUILD_TEST_UTILS})
install(TARGETS test_utils
ARCHIVE DESTINATION ${CMAKE_INSTALL_PREFIX}/runtime_lib/${AIE_RUNTIME_TARGET}/test_lib/lib
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_PREFIX}/runtime_lib/${AIE_RUNTIME_TARGET}/test_lib/include
)
endif()
install(FILES test_library.cpp DESTINATION ${CMAKE_INSTALL_PREFIX}/runtime_lib/${AIE_RUNTIME_TARGET}/test_lib/src)

set(xaienginePath ${VITIS_AIETOOLS_DIR}/include/drivers/aiengine)
# Memory Allocator

#
# Memory Allocator libraries
#

# ion memory allocator library
add_library(memory_allocator_ion STATIC memory_allocator_ion.cpp)
set(ION_PUBLIC_HEADERS
memory_allocator.h
Expand All @@ -93,7 +121,7 @@ install(TARGETS memory_allocator_ion
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_PREFIX}/runtime_lib/${AIE_RUNTIME_TARGET}/test_lib/include
)

# If we are compiling x86_64 HSA runtime, need to link against HSA
# HSA memory allocator library
if (${AIE_RUNTIME_TARGET} STREQUAL "x86_64-hsa")
add_library(memory_allocator_hsa STATIC memory_allocator_hsa.cpp)
set_target_properties(memory_allocator_hsa PROPERTIES PUBLIC_HEADER "memory_allocator.h")
Expand All @@ -113,6 +141,7 @@ if (${AIE_RUNTIME_TARGET} STREQUAL "x86_64-hsa")
)
endif()

# simulation memory allocator library
if (VITIS_ROOT)
add_library(memory_allocator_sim_aie STATIC memory_allocator.cpp)
target_compile_options(memory_allocator_sim_aie PRIVATE -fPIC)
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15 changes: 15 additions & 0 deletions runtime_lib/test_lib/test_utils.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,21 @@ std::vector<uint32_t> test_utils::load_instr_sequence(std::string instr_path) {
return instr_v;
}

std::vector<uint32_t> test_utils::load_instr_binary(std::string instr_path) {
std::ifstream instr_file(instr_path);
if (!instr_file.is_open()) {
throw std::runtime_error("Unable to open instruction file\n");
}
// read size of file, reserve space in instr_v, then read the file into
// instr_v
instr_file.seekg(0, instr_file.end);
int size = instr_file.tellg();
instr_file.seekg(0, instr_file.beg);
std::vector<uint32_t> instr_v(size / 4);
instr_file.read(reinterpret_cast<char *>(instr_v.data()), size);
return instr_v;
}

// --------------------------------------------------------------------------
// XRT
// --------------------------------------------------------------------------
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1 change: 1 addition & 0 deletions runtime_lib/test_lib/test_utils.h
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ void parse_options(int argc, const char *argv[], po::options_description &desc,
po::variables_map &vm);

std::vector<uint32_t> load_instr_sequence(std::string instr_path);
std::vector<uint32_t> load_instr_binary(std::string instr_path);

void init_xrt_load_kernel(xrt::device &device, xrt::kernel &kernel,
int verbosity, std::string xclbinFileName,
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2 changes: 1 addition & 1 deletion test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark01_DDR_SHIM_fill_rate {
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2 changes: 1 addition & 1 deletion test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark_02_LM2DDR {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/03_Flood_DDR/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark03_Flood_DDR {
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2 changes: 1 addition & 1 deletion test/benchmarks/04_Tile_Tile_FillRate/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @test04_tile_tiledma {
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2 changes: 1 addition & 1 deletion test/benchmarks/05_Core_Startup/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark05_core_startup {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/06_Buffer_Store/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark06_buffer_store {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/07_Lock_Acquire/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark07_lock_acquire {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/08_Lock_Release/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark06_lock_release {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/09_Shim_Broadcast_Horizontal/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark09_shim_broadcast {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/10_Tile_Broadcast_Horizontal/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark10_tile_broadcast_horizontal {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/11_Tile_Broadcast_Vertical/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark11_tile_broadcast_vertical {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/12_Stream_Delay/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @test12_stream_delay {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/13_Program_Counter/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark13_program_counter {
Expand Down
2 changes: 1 addition & 1 deletion test/benchmarks/14_Timer/aie.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
//
//===----------------------------------------------------------------------===//

// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf
// RUN: %run_on_board ./test.elf

module @benchmark14_timer {
Expand Down
18 changes: 15 additions & 3 deletions test/lit.cfg.py
Original file line number Diff line number Diff line change
Expand Up @@ -44,13 +44,25 @@
config.substitutions.append(
("%aie_runtime_lib%", os.path.join(config.aie_obj_root, "aie_runtime_lib"))
)
config.substitutions.append(("%aietools", config.vitis_aietools_dir))

test_lib_path = os.path.join(
config.aie_obj_root, "runtime_lib", config.aieHostTarget, "test_lib"
)
config.substitutions.append(
(
"%host_runtime_lib%",
os.path.join(config.aie_obj_root, "runtime_lib", config.aieHostTarget),
"%test_lib_flags",
f"-I{test_lib_path}/include -L{test_lib_path}/lib -ltest_lib",
)
)
config.substitutions.append(("%aietools", config.vitis_aietools_dir))
config.substitutions.append(
(
"%test_utils_flags",
"-lboost_program_options -lboost_filesystem "
+ f"-I{test_lib_path}/include -L{test_lib_path}/lib -ltest_utils",
)
)

# for xchesscc_wrapper
llvm_config.with_environment("AIETOOLS", config.vitis_aietools_dir)
# for peano clang
Expand Down
19 changes: 3 additions & 16 deletions test/npu-xrt/add_12_i8_using_2d_dma_op_with_padding/test.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -19,29 +19,16 @@
#include "xrt/xrt_device.h"
#include "xrt/xrt_kernel.h"

#include "test_utils.h"

constexpr int IN_SIZE = 61 * 56;
constexpr int OUT_SIZE = 64 * 64;

#define IN_DATATYPE int8_t
#define OUT_DATATYPE int8_t

std::vector<uint32_t> load_instr_sequence(std::string instr_path) {
std::ifstream instr_file(instr_path);
std::string line;
std::vector<uint32_t> instr_v;
while (std::getline(instr_file, line)) {
std::istringstream iss(line);
uint32_t a;
if (!(iss >> std::hex >> a)) {
throw std::runtime_error("Unable to parse instruction file\n");
}
instr_v.push_back(a);
}
return instr_v;
}

int main(int argc, const char *argv[]) {
std::vector<uint32_t> instr_v = load_instr_sequence("insts.txt");
std::vector<uint32_t> instr_v = test_utils::load_instr_sequence("insts.txt");

// Start the XRT test code
// Get a device handle
Expand Down
19 changes: 3 additions & 16 deletions test/npu-xrt/add_21_i8_using_dma_op_with_padding/test.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -19,29 +19,16 @@
#include "xrt/xrt_device.h"
#include "xrt/xrt_kernel.h"

#include "test_utils.h"

constexpr int IN_SIZE = 32;
constexpr int OUT_SIZE = 64;

#define IN_DATATYPE int8_t
#define OUT_DATATYPE int8_t

std::vector<uint32_t> load_instr_sequence(std::string instr_path) {
std::ifstream instr_file(instr_path);
std::string line;
std::vector<uint32_t> instr_v;
while (std::getline(instr_file, line)) {
std::istringstream iss(line);
uint32_t a;
if (!(iss >> std::hex >> a)) {
throw std::runtime_error("Unable to parse instruction file\n");
}
instr_v.push_back(a);
}
return instr_v;
}

int main(int argc, const char *argv[]) {
std::vector<uint32_t> instr_v = load_instr_sequence("insts.txt");
std::vector<uint32_t> instr_v = test_utils::load_instr_sequence("insts.txt");

// Start the XRT test code
// Get a device handle
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,6 @@
// REQUIRES: ryzen_ai
//
// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --aie-generate-xclbin --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++
// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags
// RUN: %run_on_npu ./test.exe aie.xclbin | FileCheck %s
// CHECK: PASS!
19 changes: 3 additions & 16 deletions test/npu-xrt/add_256_using_dma_op_no_double_buffering/test.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -19,26 +19,13 @@
#include "xrt/xrt_device.h"
#include "xrt/xrt_kernel.h"

#include "test_utils.h"

constexpr int IN_SIZE = 64;
constexpr int OUT_SIZE = 64;

std::vector<uint32_t> load_instr_sequence(std::string instr_path) {
std::ifstream instr_file(instr_path);
std::string line;
std::vector<uint32_t> instr_v;
while (std::getline(instr_file, line)) {
std::istringstream iss(line);
uint32_t a;
if (!(iss >> std::hex >> a)) {
throw std::runtime_error("Unable to parse instruction file\n");
}
instr_v.push_back(a);
}
return instr_v;
}

int main(int argc, const char *argv[]) {
std::vector<uint32_t> instr_v = load_instr_sequence("insts.txt");
std::vector<uint32_t> instr_v = test_utils::load_instr_sequence("insts.txt");

// Start the XRT test code
// Get a device handle
Expand Down
2 changes: 1 addition & 1 deletion test/npu-xrt/add_314_using_dma_op/run.lit
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// REQUIRES: ryzen_ai
//
// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --aie-generate-xclbin --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++
// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags
// RUN: %run_on_npu ./test.exe aie.xclbin | FileCheck %s
// CHECK: PASS!

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