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[wip] adjust target model to support 5x4
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bd_id pass
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@makslevental
makslevental committed Mar 7, 2024
1 parent 5164b34 commit a373505
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Showing 28 changed files with 311 additions and 316 deletions.
2 changes: 1 addition & 1 deletion include/aie/Dialect/AIE/IR/AIEDialect.h
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Original file line number Diff line number Diff line change
Expand Up @@ -233,7 +233,7 @@ typedef struct DMAChannel {
}
} DMAChannel;

const AIETargetModel &getTargetModel(mlir::Operation *op);
std::shared_ptr<AIETargetModel> getTargetModel(mlir::Operation *op);

mlir::ParseResult
parseObjectFifoProducerTile(mlir::OpAsmParser &parser,
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28 changes: 5 additions & 23 deletions include/aie/Dialect/AIE/IR/AIEInterfaces.td
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Original file line number Diff line number Diff line change
Expand Up @@ -28,13 +28,13 @@ def HasValidDMAChannels : NativeOpTrait<"HasValidDMAChannels"> {
string cppNamespace = "::xilinx::AIE";
}

def PredIsCoreTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isCoreTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
def PredIsCoreTile : CPred<"xilinx::AIE::getTargetModel(&$_op)->isCoreTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsMemTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isMemTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
def PredIsMemTile : CPred<"xilinx::AIE::getTargetModel(&$_op)->isMemTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsShimNOCTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isShimNOCTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
def PredIsShimNOCTile : CPred<"xilinx::AIE::getTargetModel(&$_op)->isShimNOCTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsShimPLTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isShimPLTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
def PredIsShimPLTile : CPred<"xilinx::AIE::getTargetModel(&$_op)->isShimPLTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;

def IsCoreTile : PredOpTrait<"op exists in a core tile", PredIsCoreTile>;
Expand Down Expand Up @@ -119,26 +119,8 @@ def TileElement : OpInterface<"TileElement", [
}];
}

def AIETarget : OpInterface<"AIETarget"> {
let description = [{
Interface for operations that model an array of AIEngine cores.
}];
let cppNamespace = "::xilinx::AIE";
let methods = [
InterfaceMethod<[{
Return the target model describing the characteristics of how this operation will be implemented.
}],
"const ::xilinx::AIE::AIETargetModel&", "getTargetModel", (ins )
>
];
}

// def OffloadingTranslationAttrTrait :
// NativeTrait<"OffloadingTranslationAttrTrait", ""> {
// let cppNamespace = "::mlir::gpu";
// }

def MyOffsetSizeAndStrideOpInterface: OpInterfaceTrait<"::xilinx::AIE::MyOffsetSizeAndStrideOpInterface"> {

}

#endif // AIE_INTERFACES
11 changes: 7 additions & 4 deletions include/aie/Dialect/AIE/IR/AIEOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ class AIE_Op<string mnemonic, list<Trait> traits = []> :


def AIE_DeviceOp: AIE_Op<"device", [
AIETarget, HasParent<"mlir::ModuleOp">,
HasParent<"mlir::ModuleOp">,
SymbolTable, SingleBlock, NoTerminator, IsolatedFromAbove
]> {
let summary = "Define an AIE design targetting a complete device";
Expand Down Expand Up @@ -55,13 +55,16 @@ def AIE_DeviceOp: AIE_Op<"device", [
```
}];

let arguments = (ins AIEDevice:$device);
let arguments = (
ins AIEDevice:$device,
DefaultValuedOptionalAttr<BoolAttr, "true">:$virtualized
);
let regions = (region AnyRegion:$body_region);
let assemblyFormat = [{
`(` $device `)` regions attr-dict
`(` $device (`,` `virtualized` `=` $virtualized^)? `)` regions attr-dict
}];
let extraClassDeclaration = [{
const xilinx::AIE::AIETargetModel &getTargetModel();
std::shared_ptr<xilinx::AIE::AIETargetModel> getTargetModel();
}];
let hasVerifier = 1;
}
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30 changes: 19 additions & 11 deletions include/aie/Dialect/AIE/IR/AIETargetModel.h
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Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,12 @@ using TileID = struct TileID {
};

class AIETargetModel {
bool virtualized;

public:
AIETargetModel() = default;
AIETargetModel(bool virtualized = true) : virtualized(virtualized) {}

bool isVirtualized() const { return virtualized; }

virtual ~AIETargetModel();

Expand Down Expand Up @@ -204,7 +208,7 @@ class AIETargetModel {

class AIE1TargetModel : public AIETargetModel {
public:
AIE1TargetModel() = default;
using AIETargetModel::AIETargetModel;

bool isCoreTile(int col, int row) const override { return row > 0; }
bool isMemTile(int col, int row) const override { return false; }
Expand Down Expand Up @@ -268,7 +272,7 @@ class AIE1TargetModel : public AIETargetModel {

class AIE2TargetModel : public AIETargetModel {
public:
AIE2TargetModel() = default;
using AIETargetModel::AIETargetModel;

AIEArch getTargetArch() const override;

Expand Down Expand Up @@ -325,7 +329,7 @@ class VC1902TargetModel : public AIE1TargetModel {
2, 3, 6, 7, 10, 11, 18, 19, 26, 27, 34, 35, 42, 43, 46, 47};

public:
VC1902TargetModel() = default;
using AIE1TargetModel::AIE1TargetModel;

int columns() const override { return 50; }

Expand All @@ -348,7 +352,7 @@ class VE2302TargetModel : public AIE2TargetModel {
llvm::SmallDenseSet<unsigned, 8> nocColumns = {2, 3, 6, 7, 10, 11};

public:
VE2302TargetModel() = default;
using AIE2TargetModel::AIE2TargetModel;

int columns() const override { return 17; }

Expand Down Expand Up @@ -400,7 +404,7 @@ class VE2802TargetModel : public AIE2TargetModel {
22, 23, 30, 31, 34, 35};

public:
VE2802TargetModel() = default;
using AIE2TargetModel::AIE2TargetModel;

int columns() const override { return 38; }

Expand Down Expand Up @@ -451,10 +455,8 @@ class VE2802TargetModel : public AIE2TargetModel {
};

class IPUTargetModel : public AIE2TargetModel {
llvm::SmallDenseSet<unsigned, 16> nocColumns = {0, 1, 2, 3};

public:
IPUTargetModel() = default;
using AIE2TargetModel::AIE2TargetModel;

int columns() const override { return 5; }

Expand All @@ -466,11 +468,17 @@ class IPUTargetModel : public AIE2TargetModel {
bool isMemTile(int col, int row) const override { return row == 1; }

bool isShimNOCTile(int col, int row) const override {
return row == 0 && nocColumns.contains(col);
if (row == 0 && !isVirtualized())
return col >= 1;
if (row == 0)
return col >= 0;
return false;
}

bool isShimPLTile(int col, int row) const override {
return row == 0 && !nocColumns.contains(col);
if (row == 0 && !isVirtualized())
return col == 0;
return false;
}

bool isShimNOCorPLTile(int col, int row) const override {
Expand Down
4 changes: 2 additions & 2 deletions include/aie/Dialect/AIE/Transforms/AIEPathFinder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -193,7 +193,7 @@ class Router {
// https://lld.llvm.org/missingkeyfunction
virtual ~Router() = default;
virtual void initialize(int maxCol, int maxRow,
const AIETargetModel &targetModel) = 0;
std::shared_ptr<AIETargetModel> targetModel) = 0;
virtual void addFlow(TileID srcCoords, Port srcPort, TileID dstCoords,
Port dstPort) = 0;
virtual bool addFixedConnection(ConnectOp connectOp) = 0;
Expand All @@ -206,7 +206,7 @@ class Pathfinder : public Router {
public:
Pathfinder() = default;
void initialize(int maxCol, int maxRow,
const AIETargetModel &targetModel) override;
std::shared_ptr<AIETargetModel> targetModel) override;
void addFlow(TileID srcCoords, Port srcPort, TileID dstCoords,
Port dstPort) override;
bool addFixedConnection(ConnectOp connectOp) override;
Expand Down
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