[AIE2] Add concat patterns for accumulators.

Xilinx · Sep 30, 2024 · b041c2d · b041c2d
1 parent 7138fcf
commit b041c2d
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diff --git a/llvm/lib/Target/AIE/AIE2InstrPatterns.td b/llvm/lib/Target/AIE/AIE2InstrPatterns.td
@@ -976,6 +976,12 @@ def : Pat<(v64i8 (concat_vectors (v32i8 VEC256:$src0), (v32i8 VEC256:$src1))),
 def : Pat<(v128i8 (concat_vectors (v64i8 VEC512:$src0), (v64i8 VEC512:$src1))),
   (v128i8 (REG_SEQUENCE VEC1024, VEC512:$src0, sub_512_lo, VEC512:$src1, sub_512_hi))>;
 
+// additional concat patters for accumulators
+def : Pat<(v8i64 (concat_vectors (v4i64 ACC256:$src0), (v4i64 ACC256:$src1))),
+  (v8i64 (REG_SEQUENCE ACC512, ACC256:$src0, sub_256_lo, ACC256:$src1, sub_256_hi))>;
+def : Pat<(v16i64 (concat_vectors (v8i64 ACC512:$src0), (v8i64 ACC512:$src1))),
+  (v16i64 (REG_SEQUENCE ACC1024, ACC512:$src0, sub_512_lo, ACC512:$src1, sub_512_hi))>;
+
 // Extract
 def : Pat<(int_aie2_ext_I256_I512 VEC512:$src, 0x0),
            (v8i32 (EXTRACT_SUBREG VEC512:$src, sub_256_lo))>;

diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-concat-vectors.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-concat-vectors.mir
@@ -126,3 +126,46 @@ body:             |
     %1:vregbank(<64 x s8>) = G_IMPLICIT_DEF
     %2:vregbank(<128 x s8>) = G_CONCAT_VECTORS %0(<64 x s8>), %1(<64 x s8>)
     PseudoRET implicit $lr, implicit %2
+...
+
+---
+name:            vconcat_1024_8x64_acc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: "", size: 128, alignment: 32 }
+body:             |
+  bb.0.entry:
+
+    ; CHECK-LABEL: name: vconcat_1024_8x64_acc
+    ; CHECK: [[DEF:%[0-9]+]]:acc256 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:acc256 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc512 = REG_SEQUENCE [[DEF]], %subreg.sub_256_lo, [[DEF1]], %subreg.sub_256_hi
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
+    %0:accregbank(<4 x s64>) = G_IMPLICIT_DEF
+    %1:accregbank(<4 x s64>) = G_IMPLICIT_DEF
+    %2:accregbank(<8 x s64>) = G_CONCAT_VECTORS %0(<4 x s64>), %1(<4 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
+
+---
+name:            vconcat_1024_16x64_acc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: "", size: 128, alignment: 32 }
+body:             |
+  bb.0.entry:
+
+    ; CHECK-LABEL: name: vconcat_1024_16x64_acc
+    ; CHECK: [[DEF:%[0-9]+]]:ebml = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:ebmh = IMPLICIT_DEF
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:acc1024 = REG_SEQUENCE [[DEF]], %subreg.sub_512_lo, [[DEF1]], %subreg.sub_512_hi
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
+    %0:accregbank(<8 x s64>) = G_IMPLICIT_DEF
+    %1:accregbank(<8 x s64>) = G_IMPLICIT_DEF
+    %2:accregbank(<16 x s64>) = G_CONCAT_VECTORS %0(<8 x s64>), %1(<8 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...