Merge pull request #969 from Xilinx/bugfix/fifo_sizing_tests

Bugfix/fifo sizing tests

tests/end2end/test_end2end_bnn_pynq.py

@@ -653,7 +653,15 @@ def test_set_fifo_depths(self, topology, wbits, abits, board):
         prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "ipgen_" + board)
         model = load_test_checkpoint_or_skip(prev_chkpt_name)
         test_fpga_part = get_build_env(board, target_clk_ns)["part"]
-        model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns))
+        if topology == "cnv" and wbits == 2 and abits == 2 and board == "Pynq-Z1":
+            # Enabling swg_exception for this single test case. Disabling the exception results in
+            # a design that exceeds the resources of the Pynq-Z1 board. In future this should be
+            # revisited and handled correctly as the swg_exception is poorly justified.
+            model = model.transform(
+                InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True)
+            )
+        else:
+            model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns))
         fifo_layers = model.get_nodes_by_op_type("StreamingFIFO")
         assert len(fifo_layers) > 0
         model.save(get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board))

tests/fpgadataflow/test_split_large_fifos.py

@@ -54,7 +54,7 @@ def fetch_test_model(topology, wbits=2, abits=2):
 def get_folding_cfg(depth=65536):
     cfg = dict()
     cfg["Defaults"] = dict()
-    for i in range(3):
+    for i in range(4):
         key = "StreamingFIFO_" + str(i)
         cfg[key] = {"depth": depth, "ram_style": "auto", "impl_style": "vivado"}
     return cfg