Merge pull request #852 from Xilinx/fix/alveo_build

Set axilite address range to a minimum of 4K

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -536,6 +536,7 @@ def apply(self, model):
        puts "CRITICAL WARNING: Unable to construct address map for $port."
     } {
        set range [expr 2**$awidth]
+       set range [expr $range < 4096 ? 4096 : $range]
        puts "INFO: Building address map for $port: 0+:$range"
        set name [get_property NAME $port]
        set addr_block [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]]