Update xuartlite_intr_example.c

.github/pull_request_template.md

@@ -0,0 +1,2 @@
+Please do not submit a Pull Request via github. Our project makes use of mailing lists for patch submission and review. For more details please see https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842172/Create+and+Submit+a+Patch
+

ThirdParty/bsp/freertos10_xilinx/data/freertos10_xilinx.mld

@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2015 - 2021 Xilinx, Inc.
+# Copyright (C) 2015 - 2022 Xilinx, Inc.
 #
 # This file is part of the FreeRTOS port.
 #
@@ -30,17 +30,17 @@ OPTION psf_version = 2.1.0 ;
 BEGIN OS freertos10_xilinx
 
 OPTION DRC = FreeRTOS_drc ;
-OPTION supported_peripherals =  (microblaze ps7_cortexa9 psu_cortexr5 psv_cortexr5 psu_cortexa53 psv_cortexa72);
+OPTION supported_peripherals =  (microblaze ps7_cortexa9 psu_cortexr5 psv_cortexr5 psu_cortexa53 psv_cortexa72 psx_cortexr52 psxl_cortexr52 psx_cortexa78 psxl_cortexa78);
 OPTION COPYFILES = all;
 OPTION NAME = freertos10_xilinx;
-OPTION VERSION = 1.11;
-OPTION DEPENDS = (standalone_v7_7);
+OPTION VERSION = 1.12;
+OPTION DEPENDS = (standalone_v8_0);
 OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group";
 OPTION DESC = "This Xilinx FreeRTOS port is based on FreeRTOS kernel version 10.4.6";
 
 # STDIN/STDOUT
-PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, psu_uart, psv_sbsauart, ps7_coresight_comp, psu_coresight_0, psv_coresight_0, psv_pmc_ppu1_mdm, axi_uartlite, axi_uart16550, mdm, iomodule);
-PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, psu_uart, psv_sbsauart, ps7_coresight_comp, psu_coresight_0, psv_coresight_0, psv_pmc_ppu1_mdm, axi_uartlite, axi_uart16550, mdm, iomodule);
+PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, psu_uart, psv_sbsauart, psx_sbsauart, psxl_sbsauart, ps7_coresight_comp, psu_coresight_0, psv_coresight_0, psv_pmc_ppu1_mdm, axi_uartlite, axi_uart16550, mdm, iomodule);
+PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, psu_uart, psv_sbsauart, psx_sbsauart, psxl_sbsauart, ps7_coresight_comp, psu_coresight_0, psv_coresight_0, psv_pmc_ppu1_mdm, axi_uartlite, axi_uart16550, mdm, iomodule);
 PARAM name = clocking, type = bool, default = false, desc = "Enable clocking support", permit = user;
 PARAM name = hypervisor_guest, type = bool, default = false, desc = "Enable hypervisor guest support for A53 64bit EL1 Non-Secure. If hypervisor_guest is not selected, BSP will be built for EL3.", permit = user;
 PARAM name = xil_interrupt, type = bool, default = false, desc = "Enable xilinx interrupt wrapper API support", permit = user;

ThirdParty/bsp/freertos10_xilinx/data/freertos10_xilinx.tcl

@@ -1,5 +1,5 @@
 
-# Copyright (C) 2015 - 2021 Xilinx, Inc.
+# Copyright (C) 2015 - 2022 Xilinx, Inc.
 #
 # This file is part of the FreeRTOS port.
 #
@@ -91,17 +91,27 @@ proc get_instance_name_from_base_value {base_value} {
 
 proc Check_ttc_ip {instance_name} {
 	set cortexa53cpu [hsi::get_cells -hier -filter "IP_NAME==psu_cortexa53"]
-	set is_versal [hsi::get_cells -hier -filter {IP_NAME=="psu_cortexa72" || IP_NAME=="psv_cortexa72"}]
+	set is_versal [hsi::get_cells -hier -filter {IP_NAME=="psu_cortexa72" || IP_NAME=="psv_cortexa72" || IP_NAME=="psxl_cortexr52" || IP_NAME=="psxl_cortexa78" || IP_NAME=="psx_cortexr52" || IP_NAME=="psx_cortexa78"}]
 
 	if {[llength $cortexa53cpu] > 0 || [llength $is_versal] > 0 } {
-		set ttc_ips [get_cell -hier -filter {IP_NAME== "psu_ttc" || IP_NAME== "psv_ttc"}]
+		set ttc_ips [get_cell -hier -filter {IP_NAME== "psu_ttc" || IP_NAME== "psv_ttc" || IP_NAME== "psx_ttc" || IP_NAME== "psxl_ttc"}]
 	} else {
 		set ttc_ips [get_cell -hier -filter {IP_NAME== "ps7_ttc"}]
 	}
 
+	set is_versal_net [hsi::get_cells -hier -filter {IP_NAME=="psxl_cortexr52" || IP_NAME=="psx_cortexr52" || IP_NAME=="psxl_cortexa78" || IP_NAME=="psx_cortexa78"}]
+
 	if { [llength $ttc_ips] != 0 } {
 		foreach ttc_ip $ttc_ips {
-			if {[string compare -nocase $ttc_ip $instance_name] == 0} {
+			if {[string compare -nocase $ttc_ip $instance_name] == 0 } {
+				set isintr [::hsm::utils::is_ip_interrupting_current_proc $ttc_ip]
+				if {$isintr == 1} {
+					return
+				} else {
+					error "FreeRTOS requires timer with interrupt enabled. $ttc_ip is not connected to interrupt controller."
+				}
+			}
+			if {[llength $is_versal_net] > 0 && [string first $instance_name $ttc_ip] != -1} {
 				set isintr [::hsm::utils::is_ip_interrupting_current_proc $ttc_ip]
 				if {$isintr == 1} {
 					return
@@ -156,6 +166,7 @@ proc generate {os_handle} {
 	set need_config_file "false"
 	set enable_sw_profile [common::get_property CONFIG.enable_sw_intrusive_profiling $os_handle]
 	set is_versal [hsi::get_cells -hier -filter {IP_NAME=="psu_cortexa72" || IP_NAME=="psv_cortexa72"}]
+	set is_versal_net [hsi::get_cells -hier -filter {IP_NAME=="psx_cortexr52" || IP_NAME=="psxl_cortexr52" || IP_NAME=="psx_cortexa78" || IP_NAME=="psxl_cortexa78"}]
 	# proctype should be "microblaze", ps7_cortexa9, psu_cortexr5 or psu_cortexa53
 	set commonsrcdir "../${standalone_version}/src/common"
 	set mbsrcdir "../${standalone_version}/src/microblaze"
@@ -188,7 +199,7 @@ proc generate {os_handle} {
 		file copy -force $entry [file join ".." "${standalone_version}" "src"]
 	}
 
-	if { $proctype == "psu_cortexa53" || $proctype == "ps7_cortexa9" || $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psv_cortexa72" } {
+	if { $proctype == "psu_cortexa53" || $proctype == "ps7_cortexa9" || $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psv_cortexa72" ||  $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52" || $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
 	        foreach entry [glob -nocomplain -types f [file join $armcommonsrcdir *]] {
 	       file copy -force $entry [file join ".." "${standalone_version}" "src"]
 	     }
@@ -201,7 +212,9 @@ proc generate {os_handle} {
 	switch $proctype {
 
 		"psu_cortexr5" -
-		"psv_cortexr5"
+		"psv_cortexr5" -
+		"psx_cortexr52" -
+		"psxl_cortexr52"
 		{
 				puts "In start copy psu_cortexr5"
 				file copy -force "./src/Makefile_psu_cortexr5" "./src/Makefile"
@@ -219,6 +232,8 @@ proc generate {os_handle} {
 				file copy -force $includedir "../${standalone_version}/src/"
 				if {[llength $is_versal] > 0} {
 				    set platformincludedir "../${standalone_version}/src/arm/ARMv8/includes_ps/platform/Versal"
+				} elseif {[llength $is_versal_net] > 0} {
+				    set platformincludedir "../${standalone_version}/src/arm/platform/versal_net"
 				} else {
 				    set platformincludedir "../${standalone_version}/src/arm/ARMv8/includes_ps/platform/ZynqMP"
 				}
@@ -243,7 +258,7 @@ proc generate {os_handle} {
 				puts $file_handle ""
 
 				#Tweak DDR addresses for versal, to be removed once proper addresses added by PCW
-				if {[llength $is_versal] > 0} {
+				if {[llength $is_versal] > 0 || [llength $is_versal_net] > 0} {
 					set platformsrcdir "../${standalone_version}/src/arm/cortexr5/platform/versal"
 				} else {
 				        set platformsrcdir "../${standalone_version}/src/arm/cortexr5/platform/ZynqMP"
@@ -256,7 +271,10 @@ proc generate {os_handle} {
 				close $file_handle
 			}
 		"psv_cortexa72" -
-		"psu_cortexa53"  {
+		"psu_cortexa53" -
+		"psx_cortexa78" -
+		"psxl_cortexa78"
+			{
 				set procdrv [hsi::get_sw_processor]
 			        set compiler [get_property CONFIG.compiler $procdrv]
 				if {[string compare -nocase $compiler "arm-none-eabi-gcc"] == 0} {
@@ -279,7 +297,9 @@ proc generate {os_handle} {
 				file copy -force [file join $arma5364srcdir platform ZynqMP xparameters_ps.h] ./src
                                 set platformsrcdir "../${standalone_version}/src/arm/ARMv8/64bit/platform/ZynqMP/gcc"
 				} else {
-				file copy -force [file join $arma5364srcdir platform versal xparameters_ps.h] ./src
+					if { $proctype == "psv_cortexa72" } {
+						file copy -force [file join $arma5364srcdir platform versal xparameters_ps.h] ./src
+					}
 				set platformsrcdir "../${standalone_version}/src/arm/ARMv8/64bit/platform/versal/gcc"
 				}
 		                foreach entry [glob -nocomplain [file join $platformsrcdir *]] {
@@ -288,14 +308,16 @@ proc generate {os_handle} {
 				file copy -force $includedir "../${standalone_version}/src/"
 				if {[llength $is_versal] > 0} {
 				    set platformincludedir "../${standalone_version}/src/arm/ARMv8/includes_ps/platform/Versal"
+				} elseif {[llength $is_versal_net] > 0} {
+				    set platformincludedir "../${standalone_version}/src/arm/platform/versal_net"
 				} else {
 				    set platformincludedir "../${standalone_version}/src/arm/ARMv8/includes_ps/platform/ZynqMP"
 				}
 				foreach entry [glob -nocomplain -types f [file join $platformincludedir *]] {
 				    file copy -force $entry "../${standalone_version}/src/includes_ps/"
 				}
 				if { $enable_sw_profile == "true" } {
-					error "ERROR: Profiling is not supported for A53/A72"
+					error "ERROR: Profiling is not supported for A53/A72/A78"
 				}
 				set pvconsoledir "../${standalone_version}/src/arm/ARMv8/64bit/xpvxenconsole"
 				set hypervisor_guest [common::get_property CONFIG.hypervisor_guest $os_handle ]
@@ -371,7 +393,7 @@ proc generate {os_handle} {
 	set makeconfig [open "../${standalone_version}/src/config.make" w]
 	file rename -force -- "../${standalone_version}/src/Makefile" "../${standalone_version}/src/Makefile_depends"
 
-	if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "ps7_cortexa9" || $proctype == "microblaze" || $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72"} {
+	if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52" || $proctype == "ps7_cortexa9" || $proctype == "microblaze" || $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72" || $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
 		puts $makeconfig "LIBSOURCES = *.c *.S"
 		puts $makeconfig "LIBS = standalone_libs"
 	}
@@ -392,14 +414,14 @@ proc generate {os_handle} {
 		file copy -force [file join src Source stream_buffer.c] ./src
 	}
 
-	if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5"} {
+	if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52"} {
 		file copy -force [file join src Source portable GCC ARM_CR5 port.c] ./src
 		file copy -force [file join src Source portable GCC ARM_CR5 portASM.S] ./src
 		file copy -force [file join src Source portable GCC ARM_CR5 port_asm_vectors.S] ./src
 		file copy -force [file join src Source portable GCC ARM_CR5 portmacro.h] ./src
 		file copy -force [file join src Source portable GCC ARM_CR5 portZynqUltrascale.c] ./src
 	}
-	if { $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72"} {
+	if { $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72" || $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
 		file copy -force [file join src Source portable GCC ARM_CA53 port.c] ./src
 		file copy -force [file join src Source portable GCC ARM_CA53 portASM.S] ./src
 		file copy -force [file join src Source portable GCC ARM_CA53 port_asm_vectors.S] ./src
@@ -469,7 +491,7 @@ proc generate {os_handle} {
 	puts $bspcfg_fh " * distinguish between standalone BSP and FreeRTOS BSP."
 	puts $bspcfg_fh " */"
 	puts $bspcfg_fh "#define FREERTOS_BSP"
-	if { $proctype == "psv_cortexa72"} {
+	if { $proctype == "psv_cortexa72" || $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
 		if {[string compare -nocase $compiler "arm-none-eabi-gcc"] != 0} {
 			puts $bspcfg_fh "#define EL3 1"
 			puts $bspcfg_fh "#define EL1_NONSECURE 0"
@@ -562,7 +584,7 @@ proc generate {os_handle} {
 	puts $file_handle "\n/******************************************************************/\n"
 	set val [common::get_property CONFIG.enable_stm_event_trace $os_handle]
 	if { $val == "true" } {
-		if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72" } {
+		if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52" || $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72" || $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
 			variable stm_trace_header_data
 			puts $file_handle "/* Enable event trace through STM */"
 			puts $file_handle "#define FREERTOS_ENABLE_TRACE"
@@ -894,14 +916,16 @@ proc generate {os_handle} {
 	## Add constants specific to the psu_cortexr5
 	############################################################################
 
-	if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" } {
+	if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52"} {
 
 		set val [common::get_property CONFIG.PSU_TTC0_Select $os_handle]
 		if {$val == "true"} {
 			set have_tick_timer 1
 			if { $proctype == "psv_cortexr5" } {
 				set instance_name [get_instance_name_from_base_value "FF0E0000"]
 				Check_ttc_ip $instance_name
+			} elseif { $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52"} {
+				Check_ttc_ip "ttc_0"
 			} else {
 				Check_ttc_ip "psu_ttc_0"
 			}
@@ -936,6 +960,8 @@ proc generate {os_handle} {
 				if { $proctype == "psv_cortexr5" } {
 					set instance_name [get_instance_name_from_base_value "FF0F0000"]
 					Check_ttc_ip $instance_name
+				} elseif { $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52"} {
+					Check_ttc_ip "ttc_1"
 
 				} else {
 					Check_ttc_ip "psu_ttc_1"
@@ -972,6 +998,8 @@ proc generate {os_handle} {
 				if { $proctype == "psv_cortexr5" } {
 					set instance_name [get_instance_name_from_base_value "FF100000"]
 					Check_ttc_ip $instance_name
+				} elseif { $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52"} {
+					Check_ttc_ip "ttc_2"
 				} else {
 					Check_ttc_ip "psu_ttc_2"
 				}
@@ -1007,6 +1035,9 @@ proc generate {os_handle} {
 				if { $proctype == "psv_cortexr5" } {
 					set instance_name [get_instance_name_from_base_value "FF110000"]
 					Check_ttc_ip $instance_name
+				} elseif { $proctype == "psx_cortexr52" || $proctype == "psxl_cortexr52"} {
+					set instance_name [get_instance_name_from_base_value "F1DF0000"]
+					Check_ttc_ip "ttc_3"
 				} else {
 					Check_ttc_ip "psu_ttc_3"
 				}
@@ -1064,15 +1095,17 @@ proc generate {os_handle} {
 	## Add constants specific to the psu_cortexa53
 	############################################################################
 
-	if { $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72" } {
+	if { $proctype == "psu_cortexa53" || $proctype == "psv_cortexa72" || $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
 
 		set val [common::get_property CONFIG.PSU_TTC0_Select $os_handle]
 		if {$val == "true"} {
 			set have_tick_timer 1
 			if { $proctype == "psv_cortexa72" } {
 				set instance_name [get_instance_name_from_base_value "FF0E0000"]
 				Check_ttc_ip $instance_name
-			} else {
+			} elseif { $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
+                                          Check_ttc_ip "ttc_0"
+                        } else {
 				Check_ttc_ip "psu_ttc_0"
 			}
 			set val1 [common::get_property CONFIG.PSU_TTC0_Select_Cntr $os_handle]
@@ -1106,6 +1139,8 @@ proc generate {os_handle} {
 			if { $proctype == "psv_cortexa72" } {
 				set instance_name [get_instance_name_from_base_value "FF0F0000"]
 				Check_ttc_ip $instance_name
+			} elseif { $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
+                                          Check_ttc_ip "ttc_1"
 			} else {
 				Check_ttc_ip "psu_ttc_1"
 			}
@@ -1141,9 +1176,11 @@ proc generate {os_handle} {
 				if { $proctype == "psv_cortexa72" } {
 					set instance_name [get_instance_name_from_base_value "FF100000"]
 					Check_ttc_ip $instance_name
-			} else {
-				Check_ttc_ip "psu_ttc_2"
-			}
+				} elseif { $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
+                                          Check_ttc_ip "ttc_2"
+				} else {
+					Check_ttc_ip "psu_ttc_2"
+				}
 				set val1 [common::get_property CONFIG.PSU_TTC2_Select_Cntr $os_handle]
 				if {$val1 == "0"} {
 					xput_define $config_file "configTIMER_ID" "XPAR_XTTCPS_6_DEVICE_ID"
@@ -1176,6 +1213,8 @@ proc generate {os_handle} {
 			if { $proctype == "psv_cortexa72" } {
 				set instance_name [get_instance_name_from_base_value "FF110000"]
 				Check_ttc_ip $instance_name
+			} elseif { $proctype == "psx_cortexa78" || $proctype == "psxl_cortexa78"} {
+                                          Check_ttc_ip "ttc_3"
 			} else {
 				Check_ttc_ip "psu_ttc_3"
 			}