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Fixed FPU/SIMD accessibility for EL1 execution #100

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a63b57d
sw_apps :versal_pmcfw: Rectify the npi blk values as per cdo v2 spec
Mar 11, 2019
6b19345
cpu_cortexa72: Support IP name psv_cortexa72
mubinsyed Mar 11, 2019
e67183e
sw_apps:versal_plm: Correct initialization of image id for PLM CDO
Mar 11, 2019
b86efad
xillibpm: add support for subsystem id passed by PLM
Mar 11, 2019
e627846
v_hdmiphy1: Updates for Versal GTYE5
Mar 13, 2019
71270ec
usbpsu: examples: Update index and readme files
Mar 12, 2019
4d9e6a4
wdttb:examples:Added versal support
Mar 12, 2019
e181d93
freertos10_xilinx: Add support for hard float in R5 freertos port
Mar 11, 2019
51f5aaf
sw_services :xilloader: variable used before assignment.
Mar 12, 2019
365bbe9
sw_apps: zynqmp_fsbl: Select EEPROM Lower Page for reading SPD data
mnarani Mar 12, 2019
6f6e8e5
lwip211: Fix BYTE_ORDER redefined warning
radheyxilinx Mar 12, 2019
93c75e7
lwip211: Fix gcc warnings in emaclite adapter source
radheyxilinx Mar 12, 2019
9716a5a
lwip211: Fix emaclite xemacliteif_input freertos implementation
radheyxilinx Mar 12, 2019
e611bf9
sw_apps :versal_pmcfw: Fix bug in ScanClearPass function
Mar 13, 2019
ea498b4
sw_apps :versal_plm: Variable used before assignment.
Mar 13, 2019
14c81d1
sw_services :xilpdi: variable used before assignment.
Mar 12, 2019
2e1f818
Add support for versal IP naming
Mar 11, 2019
f0250b7
cfupmc: Add support for psv_pmc_cfu_apb IP name
Mar 13, 2019
a8d964f
cframe: Add support for psv_pmc_cfi_cframe IP name
Mar 13, 2019
5560b7b
sysmonpsv: Macro to return interrup ALARM mask
Mar 1, 2019
0bbd069
sysmonpsv: API to set Supply for a New Data interrupt
Mar 1, 2019
149d0cc
xillibpm: Extern C added to header files
Mar 11, 2019
efcedfb
xilpm: Extern C added to header files
Mar 11, 2019
d7b7855
openamp: update to match upstream up to commit 83f2b72
Mar 5, 2019
4154dcb
openamp_echo_test: zynqmp_r5: use different shared memory based on RP…
Mar 5, 2019
38dce47
openamp_matrix_multiply: zynqmp_r5: use different shared memory based…
Mar 5, 2019
874a9d1
openamp_rpc_demo: zynqmp_r5: use different shared memory based on RPU id
Mar 5, 2019
62d98a2
Xilskey: Add assert to validate lengths in XilSKey_Efuse_ValidateKey()
Mar 13, 2019
a39a997
v_hdmiphy1: Minor bug fix
Mar 13, 2019
3f2da8c
XilSecure: Refactoring h/w definitions
Mar 13, 2019
0532856
XilSecure: SHA3 is refactored
Mar 13, 2019
ef8dc94
XilSecure: Refactoring AES driver
Mar 13, 2019
fa62c32
XilSecure: RSA functionality refactoring
Mar 13, 2019
14444ee
XilSecure: Refactored xsecure file
Mar 13, 2019
bdd52f3
tmr_manager: makefile: Add "ASSEMBLY_OBJECTS" for compilation of asse…
Mar 13, 2019
9d27eef
sysmonpsv: modified macro functions to inline functions
Mar 13, 2019
fef6747
sysmonpsv: modify the driver supported peripheral entry
Mar 13, 2019
8ebba42
sysmonpsv: add a sysmon polled example
Mar 13, 2019
9d766e2
sw_services :xilplmi: attempt to use uninitialised pointer.
Mar 15, 2019
6d2e247
iicps: Added arbitration lost support
Mar 13, 2019
318dcab
iicps: Updated Copyright year and addtogroup
Mar 13, 2019
b4a3c0f
BSP:cortexr5: Fix warnings related to last line of files
mubinsyed Mar 11, 2019
f5c69c3
BSP: Fix warnings related to undefined preprocessing identifiers
mubinsyed Mar 11, 2019
7272530
sw_apps:versal_pmcfw: Added psv_pmc IP name for PMiC MB processor
Mar 13, 2019
9e0f133
sw_apps:versal_psm: Added psv_psm IP name for PSM MB
Mar 13, 2019
bec1a74
xillibpm: Added psv_* IP names for PMC and PSM MB processor name
Mar 13, 2019
9b5a58a
xilloader: Added psv_* IP names for PMC and PSM MB processor name
Mar 13, 2019
31a4951
mbox: Added psv_* IP names for PMC and PSM MB processor name
Mar 13, 2019
fa8ccfd
xilplmi: Added psv_* IP names for PMC and PSM MB processor name
Mar 13, 2019
30bc629
rfdc: Invert clock detect bits
Mar 14, 2019
ed326fd
rfdc: The Fix XRFdc_GetPLLConfig bug
Mar 14, 2019
b3d8b5d
openamp examples: add errno.h to where errno is used
Mar 15, 2019
dffebd2
v_multi_scaler_l2: Corrected argument type for arrays of SRC and DST …
Mar 15, 2019
980c75e
sw_apps: Clean up freertos_hello_world copyright text
mubinsyed Mar 7, 2019
57e0069
XilSecure: Add input validations for Xsecure API's
Mar 15, 2019
0e0c900
XilSecure: Adds sha3 state to the sha3 Instance.
Mar 15, 2019
41216cb
XilSecure: Adds Aes state to AesInstance.
Mar 15, 2019
e0195b5
XilSecure: Adds Rsa state to RsaInstance.
Mar 15, 2019
86f326c
sw_apps :versal_pmcfw: Enable SBI_DATARDY interrupt in PMCFW
Mar 16, 2019
e439dc7
sw_apps:versal_plm: Increased stack size and enabled stack protection
Mar 15, 2019
d56ed99
sw_services:xilplmi: Added error values in comments for readability
Mar 15, 2019
79b6d75
sw_services:xilloader: Added support for loading partial PDIs
Mar 15, 2019
aece882
ospipsv: Added Cache Invalidate after DMA read
Mar 16, 2019
e4a2961
ospipsv: Used XIL_EXCEPTION_ID_INT instead of XIL_EXCEPTION_ID_FIQ_INT
Mar 16, 2019
e785607
xilisf: Used XIL_EXCEPTION_ID_INT instead of XIL_EXCEPTION_ID_FIQ_INT
Mar 16, 2019
0b900af
hdcp22_rx_dp: Added Rx Capability set API
Mar 18, 2019
3dc664e
dp14txss: Corrected HDCP22 functions
Mar 14, 2019
18183fc
dp14rxss: Corrected HDCP22 functions
Mar 14, 2019
6b200c3
hdcp22_tx_dp: Corrected driver version number.
Mar 14, 2019
3936759
Removed obsolete drivers v_pt4175, v_pt3190, v_dpt4175, v_dpt3190
saddepal Mar 18, 2019
200ff55
xillibpm: Add Bisr repair routines
Mar 18, 2019
148ac85
xillibpm: Add Bisr function calls for house cleaning routines
Mar 18, 2019
d52c20f
xillibpm: correct NPD Mbist sequence
Mar 18, 2019
c058253
xillibpm: Add Gty and CPM house cleaning
Mar 18, 2019
e411443
xillibpm: Add missing PL house cleaning
Mar 18, 2019
629f92d
gpiops:examples:Added example for versal
sneeli-git Mar 16, 2019
69d6a04
ChangeLog:Updated Changelog file for gpiops
sneeli-git Mar 16, 2019
b30d50d
zdma: Update writeonly mode example to support versal adma IP
kedareswararao Mar 18, 2019
3defb0f
ddrpsv: Add initial version
mubinsyed Mar 16, 2019
968bb70
xillibpm: Move HB bisr before Bram/Uram bisr for PL
Mar 18, 2019
6754405
xillibpm: Remove PLD house clean post processing and add Compile flag…
Mar 19, 2019
3c00b34
Fix for xdbg_printf issue and other compilation fix. CR-1024388
Mar 12, 2019
e0871a7
sw_apps :versal_pmcfw: Global sequence init should not be called in P…
Mar 19, 2019
766cce4
Xilsecure: Added IAR support
Mar 18, 2019
21fa7d8
XilSecure: Handle XSecure_Aes Error codes properly.
Mar 20, 2019
85bdff8
Setting RX link capability to 8.1 for all RX applications
Mar 20, 2019
7762bd3
examples: generic: zynqmp_r5: use atomic_flag for flags
Mar 19, 2019
bb93bcb
examples: generic: zynqmp_r5: ipi_shmem: not clear shmem
Mar 19, 2019
38959c4
sw_apps :versal_pmcfw: Global signals enabling should not happen mult…
Mar 20, 2019
272b4f4
Xilsecure: Add timeouts in SHA module
Mar 20, 2019
08058b8
Xilsecure: Change default status value as XST_FAILURE
Mar 20, 2019
b40c201
Xilsecure: Add Status and timeout in AES
Mar 20, 2019
baf681f
Xilsecure: Read return status of the functions
Mar 20, 2019
c204b97
xillibpm: Add ADMA, RTC and IPI nodes
rajanv-xilinx Mar 20, 2019
5cbb22d
hdcp22_common: Makefile change to make map file consistent
Mar 19, 2019
ac87620
hdcp22_rng: Makefile change to make map file consistent
Mar 19, 2019
1369f6b
hdcp22_mmult: Makefile change to make map file consistent
Mar 19, 2019
fc8bd26
hdcp22_cipher_dp: Makefile change to make map file consistent
Mar 19, 2019
ff6bb97
hdcp22_rx_dp: Makefile change to make map file consistent
Mar 19, 2019
495f26c
hdcp22_tx_dp: Makefile change to make map file consistent
Mar 19, 2019
04dce1f
v_multi_scaler: Makefile change to make map file consistent
Mar 19, 2019
e9c21fa
v_frmbuf_wr: Generate consistent linker .map files across OS platforms
Mar 19, 2019
8d6cf5b
v_scenechange: Generate consistent linker .map files across OS platforms
Mar 19, 2019
9ce4ef6
mipicsiss: Generate consistent linker .map files across OS platforms
Mar 19, 2019
037e6b6
v_mix: Generate consistent linker .map files across OS platforms
Mar 19, 2019
daf35b3
dphy: Generate consistent linker .map files across OS platforms
Mar 19, 2019
6be9c98
v_frmbuf_rd: Generate consistent linker .map files across OS platforms
Mar 19, 2019
52654b4
v_hcresampler: Generate consistent linker .map files across OS platforms
Mar 19, 2019
aa09d8f
v_vcresampler: Generate consistent linker .map files across OS platforms
Mar 19, 2019
535e7b8
v_hscaler: Generate consistent linker .map files across OS platforms
Mar 19, 2019
af1d927
v_vscaler: Generate consistent linker .map files across OS platforms
Mar 19, 2019
19e8be9
v_letterbox: Generate consistent linker .map files across OS platforms
Mar 19, 2019
e3cc444
v_tpg: Generate consistent linker .map files across OS platforms
Mar 19, 2019
f2aecf0
v_csc: Generate consistent linker .map files across OS platforms
Mar 19, 2019
ef25ea0
v_deinterlacer: Generate consistent linker .map files across OS platf…
Mar 19, 2019
c51222f
csi2tx: Generate consistent linker .map files across OS platforms
Mar 19, 2019
33207a8
csi2txss: Generate consistent linker .map files across OS platforms
Mar 19, 2019
92dae4f
csi: Generate consistent linker .map files across OS platforms
Mar 19, 2019
eaac913
dsitxss: Generate consistent linker .map files across OS platforms
Mar 19, 2019
6aeedc5
dsi: Generate consistent linker .map files across OS platforms
Mar 19, 2019
4092cbb
sdi_common: Generate consistent linker .map files across OS platforms
Mar 19, 2019
13279de
v_sdirx: Generate consistent linker .map files across OS platforms
Mar 19, 2019
46a08f5
v_sditx: Generate consistent linker .map files across OS platforms
Mar 19, 2019
dedc646
v_sditxss: Generate consistent linker .map files across OS platforms
Mar 19, 2019
873ee41
v_gamma_lut: Generate consistent linker .map files across OS platforms
Mar 19, 2019
33ca1c7
Xilfpga: Correct the secure Iv handling logic.
Mar 22, 2019
f3c724b
lib: sw_services: xilmbox: Add versal GIC IP name in the tcl check
kedareswararao Mar 22, 2019
87be9b6
Xilskey: Fixed XilSKey_Efuse_ConvertStringToHexBE
Mar 23, 2019
8f93d81
XilSecure: Added RSA support for Versal
Mar 21, 2019
5563c1a
xilsecure: Refactored the code
Mar 24, 2019
09db79a
XilSecure: Refactored the code
Mar 24, 2019
4fba441
zynqmp_pmufw: Fixed MISRA-C violations in pm_pinctrl files
Mar 23, 2019
5c2043e
Adding support to configure user defined EDID data.
Mar 25, 2019
54d9a6a
corrected pixel width calculation for native mode
Mar 25, 2019
bae6934
xillibpm: server: Add PL SRST release to PL init sequence
Mar 28, 2019
2d0e2ae
xillibpm: server: Fix warnings
Mar 28, 2019
d365474
sw_services: xillibpm: Fixed MISRA-C violation in xpm_device_idle files
Mar 28, 2019
da8958c
sw_services: xillibpm: Fixed MISRA-C violation in xillibpm_api.c file
Mar 27, 2019
a043f27
sw_services: xillibpm: Fixed MISRA-C violation in xpm_device.c file
Mar 27, 2019
d954365
sw_services: xillibpm: Fixed MISRA-C violation in xpm_pll.c file
Mar 27, 2019
4c52144
sw_services: xillibpm: Fixed MISRA-C violation in xpm_device_idle.c file
Mar 27, 2019
fc555a4
sw_services: xillibpm: Fixed MISRA-C violation in xpm_ipi.c file
Mar 27, 2019
8c5cca4
sw_services: xillibpm: Fixed MISRA-C violation in xpm_subsystem.c file
Mar 27, 2019
8e45ed3
Xilsecure:Procedure contains UR data flow anomalies.
Mar 28, 2019
87342cf
Xilsecure:Copy source parameter not checked before use.
Mar 28, 2019
82351fd
Xilsecure:Macro parameter not in brackets.
Mar 28, 2019
41a2614
Xilsecure:Function return type inconsistent.
Mar 28, 2019
4f6e1a5
Xilsecure:Expression is not Boolean.
Mar 28, 2019
7f8c002
Xilsecure:Implicit conversion of underlying type (MR).
Mar 28, 2019
abdd399
Xilsecure: Literal value requires a U suffix.
Mar 28, 2019
1bd3043
Xilsecure:Expression needs brackets.
Mar 28, 2019
b5b6f28
Xilsecure: (void) missing for discarded return value.
Mar 28, 2019
d5d0fa5
Xilsecure:Signed/unsigned conversion without cast.
Mar 28, 2019
4ad6b55
Xilsecure: More than one prototype for same function.
Mar 28, 2019
d77adb8
Xilsecure: Prototype and definition name mismatch.
Mar 28, 2019
dc4af98
Xilsecure: Implicit conversion: actual to formal param (MR).
Mar 28, 2019
3c99a61
Xilsecure:Use of mixed mode arithmetic.
Mar 28, 2019
ec2fd6d
Xilsecure: Use of underlying enum representation value.
Mar 28, 2019
33cf3d2
Xilsecure: Removed unnecessary code
Mar 28, 2019
0db1e36
Xilsecure: Added extern C
Mar 28, 2019
d155f9c
sw_apps: pmufw: Fix pmu-firmware build failure in vless flow
kedareswararao Mar 27, 2019
3049d3d
sw_services :xilloader: Handoff must only happen once for a processor
Mar 29, 2019
e81fe2c
ddrpsv: Tweak cortexr5 view for lower DDR
mubinsyed Mar 29, 2019
1e37db6
XilSecure: Added support for ECDSA
Mar 28, 2019
8cd5c87
xilfpga:src:MISRA-C:No brackets to loop body.
Mar 29, 2019
637cb22
xilfpga:updated change history
Mar 29, 2019
1aa60e2
BSP: microblaze: Fix exception handlers for 64 bit variant
asserhall Mar 28, 2019
c8ff552
XilSecure: Added failure condition
Mar 30, 2019
888537c
XilSecure: Removes incorrect #define XSECURE_IV_SIZE.
Mar 30, 2019
b8d87bb
XilSecure: Made CsuDma global variable as static global.
Mar 30, 2019
52211ba
xillibpm: server: Add support for clk flags
rajanv-xilinx Mar 30, 2019
f68b95a
xillibpm: server: Remove invalid clock checks
rajanv-xilinx Mar 30, 2019
35d3fb0
xillibpm: Put cores into reset after power down
Mar 30, 2019
c491123
doc: Updated qspips driver changelog
Mar 28, 2019
34baba9
ospipsv: Fixed data alignment issues for IAR compiler.
Mar 29, 2019
13f85fc
doc: Update ospipsv driver changelog for IAR fixes.
Mar 29, 2019
04c7b15
Changelog: Update changelog for prc driver
Mar 29, 2019
77e42a4
xillibpm: Extern C added to remaining header files
Mar 19, 2019
b229b43
Xilskey: Added support for user configurable GPIO
Mar 29, 2019
581031a
xilfpga: Remove vesal platform related changes
Mar 30, 2019
21e2f74
Revert "xilfpga: Remove vesal platform related changes"
saddepal Mar 31, 2019
4384a0a
freertos10_xilinx: Add configUSE_TASK_FPU_SUPPORT for A53 processor.
Mar 27, 2019
50ee0d4
sw_services :xilloader: Remove code referencing xilfpga APIs from xil…
Apr 1, 2019
fb47a10
xilfpga: Remove vesal platform related changes
Mar 30, 2019
c811da3
usbpsu: Fix incorrect dma_alignment pragma directive for IAR workbench
Mar 26, 2019
596d22f
xilffs: Fix data alignment issues for IAR compiler
mnarani Apr 1, 2019
928f145
qspipsu: Fixed data alignment warnings in the examples for IAR compiler.
Mar 26, 2019
5d06230
xillibpm: make ADMA non-secure during device request
rajanv-xilinx Apr 2, 2019
c31cb79
zynqmp_pmufw: Add support for Ultra96 power button
Apr 3, 2019
10c217a
v_scenechange: Added OBJECTS macro for compilation
Apr 4, 2019
1fe38e4
v_sdirxss: Added OBJECTS defination in Makefile
Apr 4, 2019
dac282e
lib: Argument of strlen is unterminated.
Apr 4, 2019
aae0459
dp14: Adding MST-Lite Audio Enable/Disable support
Apr 8, 2019
68ab0a9
sw_apps: memtest: Add check for Carriage return for manual size test
mnarani Apr 9, 2019
84f60a0
Xilsecure: Fixed IAR warning
Apr 8, 2019
ac8cf31
This patch updates the MST passthrough application and TX audio for S…
Apr 9, 2019
1fe86da
dp14rxss: Adding support to new firmware version of mcdp retimer.
Apr 8, 2019
6ab3dfc
XilSecure: Use XCsuDma_WaitForDoneTimeOut instead of XCsuDma_WaitForD…
Apr 9, 2019
8e04ffd
xilfpga: Fixed IAR compiler warnings in read back examples
Apr 3, 2019
0bdaad1
vprocss: Provide programmable fps for the application
Apr 9, 2019
0b6177a
xillibpm: server: Change set requirement logic
rajanv-xilinx Apr 10, 2019
dcec3ae
xillibpm: server: Change subsystem state after resume
rajanv-xilinx Apr 10, 2019
b7262a6
xillibpm: server: Skip reset assert for peripheral devices
Apr 10, 2019
81abc9b
versal_psmfw: Remove XPsmFwGemDisable() from xpsmfw_power.c
Apr 10, 2019
37668c6
xillibpm: Changed psu to psv
Apr 4, 2019
c776672
video_common: Modified APIs to take more than 32 bit value
Apr 11, 2019
808f6f7
xillibpm: Add CoreOps for setting resume address
Apr 9, 2019
8076eac
xillibpm: Set resume address only after parent power up
Apr 9, 2019
309fa39
xillibpm: consider POWER_UP_SELF state as POWER OFF state
Apr 5, 2019
b472b4f
xilloader: Add support to reload the image partition only
Apr 5, 2019
5beb1fd
xillibpm: Reload FPD CDO after powering on FPD
Apr 9, 2019
047ceb7
sw_apps: memtest: Split the Cache Invalidation for lower and Upper DDR
mnarani Apr 12, 2019
d182b4a
sw_apps: memtest: Simplify the User Interface for Memtest
mnarani Apr 12, 2019
5ac9bef
XilSecure: Resolves cache issue seen with static global variables.
Apr 10, 2019
36a219f
Added psm_fw.elf
saddepal Apr 12, 2019
f84c76f
xillibpm: server: Return if clock state is already in desired state
rajanv-xilinx Apr 11, 2019
ca75716
rfdc: Fixed bug where Internal PLL enabled was wrong for below Gen 3 IPs
Apr 9, 2019
61c9636
rfdc: Fixed bug where tile was not restarting after PLL rate change
Apr 9, 2019
ed8a841
v_hdmiphy1: DRU Center Frequency configuration is wrong when RX is us…
Apr 15, 2019
21a8ac6
This patch resolves the 8K syntax error. Updates made to audio inforf…
Apr 15, 2019
48c7c61
v_frmbuf_rd: Correct the format order in config structure
Apr 15, 2019
b4d61e2
sw_services:xilplmi: Fixed the DMA offset issue
Apr 16, 2019
a89c825
Updated the si5324_LOL_GPIO to si5324_LOL1_GPIO
Apr 16, 2019
c73bf8f
Updated user pixel width calculation for dual pixel mode.
Apr 17, 2019
babf8c7
pciepsu: Adds config check for running examples
Mar 15, 2019
05ab95f
pciepsu: Adds Endpoint code
Mar 15, 2019
22e195d
pciepsu: Fix checkpatch warnings
Apr 16, 2019
0433e1a
pciepsu: Add 64-bit destination address support for ingress setup
Apr 16, 2019
f848ef8
pciepsu: Bar assignment bug fix
Apr 16, 2019
0f3ec31
versal_psmfw: Migrate from PSU to PSV
Apr 17, 2019
7d8a27f
sw_apps: memtest: Handle cache invalidation for Upper DDR in Eye Tests
mnarani Apr 17, 2019
c4db7a0
xdprxss: Removed ACR.Adding 422 420 and RGB 8 bit 10 bi support
Apr 15, 2019
a0a4de0
video_common: Reverted the patch titled Modified APIs to take more th…
Apr 18, 2019
7629123
Issue Resolve :- After Retraining somtimes HDCP 1.3 Encryption does n…
Apr 19, 2019
5190d82
lib: standalone: Update PS IP definition macros to migrate from PSU t…
kedareswararao Apr 19, 2019
b7a931d
xillibpm: server: Allow INVALID_SUBSYTEMID to be set
Apr 22, 2019
9c13a92
standalone: Added frequently used common functions
Apr 25, 2019
1b3aeb2
xilplmi: Modified OSPI protection macros
Apr 26, 2019
59b8270
lib: Add support for armclang compiler in xilpm makefile
Apr 30, 2019
e58b116
This patch fixes the RX linereset disable issue for 4K@120 resolution…
May 1, 2019
4491d5e
gpio:example:updated example file for versal.
May 1, 2019
6f06bde
gpio:src:Updated Makefile for IAR
Apr 29, 2019
6e015c4
standalone: Fixed armcc compiler specific error
May 4, 2019
07af3d8
xilmailbox: Rename the library
kedareswararao May 6, 2019
238061c
Updated version number for xilpm in doc/ChangeLog
saddepal May 7, 2019
06bbf6d
Updated to have latest copyright information
saddepal Mar 8, 2019
2ab0ce7
xilffs: Remove Xilinx Copyright and License text from FatFS source
mnarani May 22, 2019
81c06e0
Fixed Rebase Conflicts
Jun 7, 2019
c12743e
Generated Doxygen documentation and PDF's for sw_services
saddepal Jun 7, 2019
2a094d0
Fixed FPU/SIMD accessibility for FreeRTOS BSP at aarch64 EL1 execution
Oct 31, 2019
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150 changes: 55 additions & 95 deletions README.txt
Original file line number Diff line number Diff line change
@@ -1,149 +1,109 @@
embeddedsw.git - repo for standalone software

All software is version less and divided into three directories
The standalone software is divided into following directories:
- lib
contains bsp, zynq fsbl and software services like xilisf
contains bsp, software apps and software services
- license.txt
contains information about the various licenses and copyrights
- XilinxProcessorIPLib
- doc/ChangeLog
Contains change log information for releases
- XilinxProcessorIPLib/drivers
contains all drivers
- ThirdParty
software from third party like light weight IP stack
- mcap
- mcap/linux
software for using MCAP interface on Ultra Scale boards to
program 2nd level bitstream

Every driver/lib/apps/services has these sub-directories

Every driver, sw_apps and sw_services has one or more of these sub-directories:
1. data - contains tcl, mdd, testapp tcl or header files used in SDK
2. doc - documentation of source code in form of pdf or html
2. doc - documentation of source code in form of pdf or html
3. examples - illustrating different use cases of driver
4. src - driver interface code implementing functionality of IP


<repo>
|-XilinxProcessorIPLib
| |- drivers
| |- uartps
|-ThirdParty
| |- bsp
| |- freertos1-_xilinx
| |- data
| |- src
| |- doc
| |- examples
| |- License
| |- Source
| |- sw_services
| |- libmetal
| |- lwip141
| |- lwip202
| |- openamp
|
|-XilinxProcessorIPLib
| |- drivers
| |- avbuf
| |- ...
| |- ...
| |- zdma
|
|-doc
|-lib
| |- bsp
| |- standalone
| |- data
| |- doc
| |- src
| |- arm
| |- common
| |- cortexa9
| |- cortexa53
| |- cortexr5
| |- arm
| |- common
| |- cortexa53
| |- cortexa9
| |- cortexr5
| |- common
| |- microblaze
| |- common
| |- profile
| |- doc
| |- xilkernel
| |- data
| |- doc
| |- src
| |- sw_apps
| |- zynq_fsbl [described below]
|- zynqmp_fsbl [described below]
|- zynqmp_pmufw [described below]
| |- ddr_self_refresh
| |- ....
| |- ....
| |- ....
| |- ....
| |- zynqmp_fsbl [described below]
| |- zynqmp_pmufw [described below]
| |- sw_services
| |- xilffs
| |- xilskey
| |- xilmfs
| |- xilrsa
| |- xilflash
| |- xilfpga
| |- xilisf
| |- xilmfs
| |- xilpm
| |- xilrsa
| |- xilsecure
| |- xilskey
|
| Note - All these are libraries and utilize drivers
|
|-ThirdParty
| |- sw_services
| |- lwip140
|
|-mcap
| |-linux


Building FSBL from git:

==============================
FSBL(zynq_fsbl/zynqmp_fsbl) has 3 directories.
1. data - It contains files for SDK
2. src - It contains the FSBL source files
3. misc - It contains miscellaneous files required to
compile FSBL.
For zynq (zynq_fsbl), builds for zc702, zc706, zed and
microzed boards are supported.
For zynqmp (zynqmp_fsbl), builds for zcu102,zcu102-es2 board are
supported.
For zynq (zynq_fsbl), builds for zc702, zc706, zed are supported.
It also contains the ps7_init_gpl.[c/h] with gpl
header in respective board directories.
For zynqmp (zynqmp_fsbl), builds for zcu102,zcu102-es2 board are
supported.



How to compile FSBL:
Zynq
1.Go to the Fsbl src directory "lib/sw_apps/zynq_fsbl/src/"
2. make "BOARD=<>" "CC=<>"
a. Values for BOARD are zc702, zc706, zed, microzed
b. Value for CC is arm-xilinx-eabi-gcc. Default value is also same.
3.Give "make" to compile the fsbl with BSP. By default it is
built for zc702 board with arm-xilinx-eabi-gcc compiler
4.Below are the examples for compiling for different options
a. To generate Fsbl for zc706 board
i.make "BOARD=zc706"
b.To generate Fsbl for zc702 board with debug enable
and RSA support
i.make "BOARD=zc702" "CFLAGS=-DFSBL_DEBUG_INFO -DRSA_SUPPORT"
c.To generate Fsbl for zc706 board and compile with arm-xilinx-eabi-gcc
with MMC support
i.make "BOARD=zc706" "CC=arm-xilinx-eabi-gcc" "CFLAGS=-DMMC_SUPPORT"
Zynq:
Please refer to the steps in Readme.txt which is at lib/sw_apps/zynq_fsbl/misc/ directory

ZynqMP
1.Go to the Fsbl src directory "lib/sw_apps/zynqmp_fsbl/src/"
2.If executables and other artifacts from previous FSBL build with other
configuration (different processor/state) are present, run
make clean to delete them.
2.Give build command in the following manner.
a. make "BOARD=<>" "PROC=<>" "A53_STATE=<>"
a. Value for BOARD can be zcu102 or zcu102-es2. (Default is zcu102)
b. Value for PROC can be a53 or r5. (Default is a53)
c. Value for A53_STATE can be 64 or 32. (Default: 64)
A53_STATE is only to be given when processor is a53.
3.Give "make" to compile the fsbl with BSP. By default it is
built for zcu102 board.
4.Below are the examples for compiling for different options
a. To generate A53 64 bit Fsbl for zcu102 board
i.make "BOARD=zcu102" "PROC=a53" "A53_STATE=64"
b.To generate R5 Fsbl for zcu102 board with debug enable
i.make "BOARD=zcu102" "PROC=r5" "CFLAGS+=-DFSBL_DEBUG_INFO"
c.To generate A53 32 bit Fsbl for zcu102 board.
i.make "BOARD=zcu102" "PROC=a53" "A53_STATE=32"
d. To generate A53 64 bit Fsbl for zcu102-es2 board
i.make "BOARD=zcu102-es2" "PROC=a53" "A53_STATE=64"
e.To generate R5 Fsbl for zcu102-es2 board with debug enable
i.make "BOARD=zcu102-es2" "PROC=r5" "CFLAGS+=-DFSBL_DEBUG_INFO"
f.To generate A53 32 bit Fsbl for zcu102-es2 board.
i.make "BOARD=zcu102-es2" "PROC=a53" "A53_STATE=32"
Please refer to the steps in Readme.txt which is at lib/sw_apps/zynqmp_fsbl/misc/ directory

Building PMUFW from git:

PMUFW(zynqmp_pmufw) has 3 directories.
1. data - It contains files for SDK
2. src - It contains the PMUFW source files
3. misc - It contains miscellaneous files required to
compile PMUFW.


How to compile PMUFW:

ZynqMP
1.Go to the PMUFW src directory "lib/sw_apps/zynqmp_pmufw/src/"
2.If executables and other artifacts from previous PMUFW build are present, run
make clean to delete them.
3.Give "make" to compile the PMUFW with BSP.
==============================
Please refer to the steps in Readme.txt which is at lib/sw_apps/zynqmp_pmufw/misc/ directory
115 changes: 115 additions & 0 deletions ThirdParty/bsp/freertos10_xilinx/data/freertos10_xilinx.mld
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#
# Copyright (C) 2015 - 2019 Xilinx, Inc.
#
# This file is part of the FreeRTOS port.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy of
# this software and associated documentation files (the "Software"), to deal in
# the Software without restriction, including without limitation the rights to
# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
# the Software, and to permit persons to whom the Software is furnished to do so,
# subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
# FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
# COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
# http://www.FreeRTOS.org
# http://aws.amazon.com/freertos
#
# 1 tab == 4 spaces!
#

OPTION psf_version = 2.1.0 ;
BEGIN OS freertos10_xilinx

OPTION DRC = FreeRTOS_drc ;
OPTION supported_peripherals = (microblaze ps7_cortexa9 psu_cortexr5 psv_cortexr5 psu_cortexa53);
OPTION COPYFILES = all;
OPTION NAME = freertos10_xilinx;
OPTION VERSION = 1.3;
OPTION DEPENDS = (standalone_v7_0);
OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group";
OPTION DESC = "This Xilinx FreeRTOS port is based on FreeRTOS kernel version 10.1.1";

# STDIN/STDOUT
PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, psu_uart, ps7_coresight_comp, psu_coresight_0, iomodule, axi_uartlite, axi_uart16550, mdm);
PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, psu_uart, ps7_coresight_comp, psu_coresight_0, iomodule, axi_uartlite, axi_uart16550, mdm);

BEGIN CATEGORY kernel_behavior
PARAM name = kernel_behavior, type = bool, default = true, desc = "Parameters relating to the kernel behavior", permit = none;
PARAM name = max_api_call_interrupt_priority, type = int, default = 18, desc = "The maximum interrupt priority from which interrupt safe FreeRTOS API calls can be made.";
PARAM name = use_preemption, type = bool, default = true, desc = "Set to true to use the preemptive scheduler, or false to use the cooperative scheduler.";
PARAM name = tick_rate, type = int, default = 100, desc = "Number of RTOS ticks per sec";
PARAM name = idle_yield, type = bool, default = true, desc = "Set to true if the Idle task should yield if another idle priority task is able to run, or false if the idle task should always use its entire time slice unless it is preempted.";
PARAM name = max_priorities, type = int, default = 8, desc = "The number of task priorities that will be available. Priorities can be assigned from zero to (max_priorities - 1)";
PARAM name = minimal_stack_size, type = int, default = 200, desc = "The size of the stack allocated to the Idle task. Also used by standard demo and test tasks found in the main FreeRTOS download.";
PARAM name = total_heap_size, type = int, default = 65536, desc = "Sets the amount of RAM reserved for use by FreeRTOS - used when tasks, queues, semaphores and event groups are created.";
PARAM name = max_task_name_len, type = int, default = 10, desc = "The maximum number of characters that can be in the name of a task.";
PARAM name = use_timeslicing, type = bool, default = true, desc = "When true equal priority ready tasks will share CPU time with a context switch on each tick interrupt.";
PARAM name = use_port_optimized_task_selection, type = bool, default = true, desc ="When true task selection will be faster at the cost of limiting the maximum number of unique priorities to 32.";
END CATEGORY

BEGIN CATEGORY kernel_features
PARAM name = kernel_features, type = bool, default = true, desc = "Include or exclude kernel features", permit = none;
PARAM name = stream_buffer, type = bool, default = false, desc = "Set to true to include stream buffer functionality, or false to exclude stream buffer functionality.";
PARAM name = message_buffer, type = bool, default = false, desc = "Set to true to include message buffer functionality, or false to exclude message buffer functionality.";
PARAM name = support_static_allocation, type = bool, default = false, desc = "Set to true to allocate memory statically, or false to allocate memory dynamically.";
PARAM name = use_freertos_asserts, type = bool, default = true, desc = "Defines configASSERT() to assist development and debugging. The application can override the default implementation of vApplicationAssert( char *pcFile, uint32_t ulLine )";
PARAM name = use_mutexes, type = bool, default = true, desc = "Set to true to include mutex functionality, or false to exclude mutex functionality.";
PARAM name = use_getmutex_holder, type = bool, default = true, desc = "Set to true to use mutex xSemaphoreGetMutexHolder API, or false to exclude it.";
PARAM name = use_recursive_mutexes, type = bool, default = true, desc = "Set to true to include recursive mutex functionality, or false to exclude recursive mutex functionality.";
PARAM name = use_counting_semaphores, type = bool, default = true, desc = "Set to true to include counting semaphore functionality, or false to exclude recursive mutex functionality.";
PARAM name = queue_registry_size, type = int, default = 10, desc = "The maximum number of queues that can be registered at any one time. Only registered queues can be viewed in the Eclipse/GDB kernel aware debugger plug-in.";
PARAM name = use_trace_facility, type = bool, default = true, desc = "Set to true to include the legacy trace functionality, and a few other features. traceMACROS are the preferred method of tracing now.";
PARAM name = use_newlib_reent, type = bool, default = false, desc = "When true each task will have its own Newlib reent structure.";
PARAM name = use_queue_sets, type = bool, default = true, desc = "Set to true to include queue set functionality.";
PARAM name = use_task_notifications, type = bool, default = true, desc = "Set to true to include direct to task notification functionality.";
PARAM name = check_for_stack_overflow, type = int, default = 2, desc = "Set to 0 for no overflow checking. Set to 1 to include basic run time task stack checking. Set to 2 to include more comprehensive run time task stack checking.";
PARAM name = use_stats_formatting_functions, type = bool, default = true, desc = "Set to 1 to include the vTaskList() and vTaskGetRunTimeStats() functions, which format run-time data into human readable text.";
PARAM name = num_thread_local_storage_pointers, type = int, default = 0, desc ="Sets the number of pointers each task has to store thread local values.";
PARAM name = use_task_fpu_support, type = int, default = 1, desc ="Set to 1 to create tasks without FPU context, set to 2 to have tasks with FPU context by default.";
PARAM name = generate_runtime_stats, type = int, default = 0, desc ="Set to 1 generate runtime stats for tasks.";
END CATEGORY

BEGIN CATEGORY hook_functions
PARAM name = hook_functions, type = bool, default = true, desc = "Include or exclude application defined hook (callback) functions. Callback functions must be defined by the application that is using FreeRTOS", permit = none;
PARAM name = use_idle_hook, type = bool, default = false, desc = "Set to true for the kernel to call vApplicationIdleHook() on each iteration of the idle task. The application must provide an implementation of vApplicationIdleHook().";
PARAM name = use_tick_hook, type = bool, default = false, desc = "Set to true for the kernel to call vApplicationTickHook() during each tick interrupt. The application must provide an implementation of vApplicationTickHook().";
PARAM name = use_malloc_failed_hook, type = bool, default = true, desc = "Only used if a FreeRTOS memory manager (heap_n.c) is included in the project. Set to true for the kernel to call vApplicationMallocFailedHookHook() if there is insufficient FreeRTOS heap available for a task, queue or semaphore to be created. The application can override the default implementation of vApplicationMallocFailedHook().";
PARAM name = use_daemon_task_startup_hook, type = bool, default = false, desc = "Set true for kernel to call vApplicationDaemonTaskStartupHook on first iteration of RTOS daemon task. The application must provide an implementation of vApplicationDaemonTaskStartupHook()."
END CATEGORY

BEGIN CATEGORY software_timers
PARAM name = software_timers, type = bool, default = true, desc = "Options relating to the software timers functionality", permit = user;
PARAM name = use_timers, type = bool, default = true, desc = "Set to true to include software timer functionality, or false to exclude software timer functionality";
PARAM name = timer_task_priority, type = string, default = "(configMAX_PRIORITIES - 1)", desc = "The priority at which the software timer service/daemon task will execute.";
PARAM name = timer_command_queue_length, type = int, default = 10, desc = "The number of commands the timer command queue can hold at any one time.";
PARAM name = timer_task_stack_depth, type = string, default = "(configMINIMAL_STACK_SIZE), desc = "The size of the stack allocated to the timer service/daemon task.";
END CATEGORY

BEGIN CATEGORY tick_setup
PARAM name = tick_setup, type = bool, default = true, desc = "Configuration for enabling tick timer", permit = user;
PARAM name = PSU_TTC0_Select, type = bool, default = true, desc = "psu_cortexr5 only: Set it to true to use TTC0 for tick interrupt generation";
PARAM name = PSU_TTC0_Select_Cntr, type = int, default = 0, desc = "psu_cortexr5 only: Selects the TTC0 counter to be used for tick generation. Allowed range is 0-2";
PARAM name = PSU_TTC1_Select, type = bool, default = false, desc = "psu_cortexr5 only: Set it to true to use TTC1 for tick interrupt generation";
PARAM name = PSU_TTC1_Select_Cntr, type = int, default = 0, desc = "psu_cortexr5 only: Selects the TTC1 counter to be used for tick generation. Allowed range is 0-2";
PARAM name = PSU_TTC2_Select, type = bool, default = false, desc = "psu_cortexr5 only: Set it to true to use TTC2 for tick interrupt generation";
PARAM name = PSU_TTC2_Select_Cntr, type = int, default = 0, desc = "psu_cortexr5 only: Selects the TTC2 counter to be used for tick generation. Allowed range is 0-2";
PARAM name = PSU_TTC3_Select, type = bool, default = false, desc = "psu_cortexr5 only: Set it to true to use TTC3 for tick interrupt generation";
PARAM name = PSU_TTC3_Select_Cntr, type = int, default = 0, desc = "psu_cortexr5 only: Selects the TTC3 counter to be used for tick generation. Allowed range is 0-2";
END CATEGORY

BEGIN CATEGORY enable_stm_event_trace
PARAM name = enable_stm_event_trace, type = bool, default = false, desc = "Enable event tracing through System Trace Macrocell avaialable on Zynq MPSoC. This is supported only for Cortex A53 and R5 processors", permit = user;
PARAM name = enable_timer_tick_trace, type = bool, default = false, desc = "Enable tracing of timer tick events", permit = user;
PARAM name = stm_channel, type = int, default = 0, desc = "STM channel to use for trace. Valid channels are 0-65535";
END CATEGORY

END OS
39 changes: 39 additions & 0 deletions ThirdParty/bsp/freertos10_xilinx/data/freertos10_xilinx.mss
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#
# Copyright (C) 2015 - 2019 Xilinx, Inc.
#
# This file is part of the FreeRTOS port.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy of
# this software and associated documentation files (the "Software"), to deal in
# the Software without restriction, including without limitation the rights to
# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
# the Software, and to permit persons to whom the Software is furnished to do so,
# subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
# FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
# COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
# http://www.FreeRTOS.org
# http://aws.amazon.com/freertos
#
# 1 tab == 4 spaces!
#

PARAMETER VERSION = 2.2.0

BEGIN OS
PARAMETER OS_NAME = freertos10_xilinx
PARAMETER STDIN = *
PARAMETER STDOUT = *
PARAMETER SYSTMR_SPEC = true
PARAMETER SYSTMR_DEV = *
PARAMETER SYSINTC_SPEC = *
END

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