SystemVerilog based IEEE-754 Floating Point Division Algorithm which is direct translation of the C source file, part of the SoftFloat IEEE Floating-Point Arithmetic Package. It is synthesizable functional block of FPU divide unit tested and verified on Mentor Questa 2021.3. It works only on normal floating points not on subnormal floating point numbers.
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SystemVerilog based IEEE-754 Floating Point Division Algorithm which is direct translation of the C source file, part of the SoftFloat IEEE Floating-Point Arithmetic Package, Release 3d, by John R. Hauser.
UmerShahidengr/FP_Division
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SystemVerilog based IEEE-754 Floating Point Division Algorithm which is direct translation of the C source file, part of the SoftFloat IEEE Floating-Point Arithmetic Package, Release 3d, by John R. Hauser.
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