Update model/riscv_fdext_regs.sail

Co-authored-by: Jessica Clarke <[email protected]>
Signed-off-by: Tim Hutt <[email protected]>

model/riscv_fdext_regs.sail

@@ -39,7 +39,7 @@ function canonical_NaN_Q() -> bits(128) = canonical_NaN(128)
 val nan_box : forall 'n 'm, 'n <= 'm . (implicit('m), bits('n)) -> bits('m)
 function nan_box(n, x) = ones('m - 'n) @ x
 
-// When an n-bit float is stored ina smaller m-bit register it is "unboxed"
+// When an n-bit float is stored in a smaller m-bit register it is "unboxed"
 // - only if it is a valid boxed NaN. Otherwise a canonical NaN value is stored.
 // TODO: Use right-open interval when available. See https://github.com/rems-project/sail/issues/471
 val nan_unbox : forall 'n 'm, 'm in {16, 32, 64, 128} & 'n >= 'm . (implicit('m), bits('n)) -> bits('m)