Skip to content

Commit

Permalink
Simplify softfloat interface by removing write_fflags
Browse files Browse the repository at this point in the history 
Instead of keeping a mirror register in sync with fflags, just return the new flags.
  • Loading branch information
@Timmmm
Timmmm committed Oct 23, 2023
1 parent c90cf2e commit 2d18a15
Show file tree
Hide file tree
Showing 7 changed files with 63 additions and 79 deletions.
2 changes: 1 addition & 1 deletion c_emulator/riscv_softfloat.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ static uint_fast8_t uint8_of_rm(mach_bits rm)

#define SOFTFLOAT_POSTLUDE(res) \
zfloat_result = res.v; \
zfloat_fflags |= (mach_bits)softfloat_exceptionFlags
zfloat_fflags = (mach_bits)softfloat_exceptionFlags

unit softfloat_f16add(mach_bits rm, mach_bits v1, mach_bits v2)
{
Expand Down
12 changes: 1 addition & 11 deletions model/riscv_fdext_regs.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -528,26 +528,16 @@ val ext_write_fcsr : (bits(3), bits(5)) -> unit
function ext_write_fcsr (frm, fflags) = {
fcsr->FRM() = frm; /* Note: frm can be an illegal value, 101, 110, 111 */
fcsr->FFLAGS() = fflags;
update_softfloat_fflags(fflags);
dirty_fd_context_if_present();
}

/* called for softfloat paths (softfloat flags are consistent) */
val write_fflags : (bits(5)) -> unit
function write_fflags(fflags) = {
if fcsr.FFLAGS() != fflags
then dirty_fd_context_if_present();
fcsr->FFLAGS() = fflags;
}

/* called for non-softfloat paths (softfloat flags need updating) */
/* OR flags into the fflags register. */
val accrue_fflags : (bits(5)) -> unit
function accrue_fflags(flags) = {
let f = fcsr.FFLAGS() | flags;
if fcsr.FFLAGS() != f
then {
fcsr->FFLAGS() = f;
update_softfloat_fflags(f);
dirty_fd_context_if_present();
}
}
32 changes: 16 additions & 16 deletions model/riscv_insts_dext.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -349,7 +349,7 @@ function clause execute (F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, op)) = {
FNMSUB_D => riscv_f64MulAdd (rm_3b, negate_D (rs1_val_64b), rs2_val_64b, rs3_val_64b),
FNMADD_D => riscv_f64MulAdd (rm_3b, negate_D (rs1_val_64b), rs2_val_64b, negate_D (rs3_val_64b))
};
write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_64b;
RETIRE_SUCCESS
}
Expand Down Expand Up @@ -413,7 +413,7 @@ function clause execute (F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, op)) = {
FMUL_D => riscv_f64Mul (rm_3b, rs1_val_64b, rs2_val_64b),
FDIV_D => riscv_f64Div (rm_3b, rs1_val_64b, rs2_val_64b)
};
write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_64b;
RETIRE_SUCCESS
}
Expand Down Expand Up @@ -501,7 +501,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FSQRT_D)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_D) = riscv_f64Sqrt (rm_3b, rs1_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_D;
RETIRE_SUCCESS
}
Expand All @@ -516,7 +516,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_W_D)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_W) = riscv_f64ToI32 (rm_3b, rs1_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend (rd_val_W);
RETIRE_SUCCESS
}
Expand All @@ -531,7 +531,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_WU_D)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_WU) = riscv_f64ToUi32 (rm_3b, rs1_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend (rd_val_WU);
RETIRE_SUCCESS
}
Expand All @@ -546,7 +546,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_W)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_D) = riscv_i32ToF64 (rm_3b, rs1_val_W);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_D;
RETIRE_SUCCESS
}
Expand All @@ -561,7 +561,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_WU)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_D) = riscv_ui32ToF64 (rm_3b, rs1_val_WU);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_D;
RETIRE_SUCCESS
}
Expand All @@ -576,7 +576,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_S_D)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_S) = riscv_f64ToF32 (rm_3b, rs1_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_S;
RETIRE_SUCCESS
}
Expand All @@ -591,7 +591,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_S)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_D) = riscv_f32ToF64 (rm_3b, rs1_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_D;
RETIRE_SUCCESS
}
Expand All @@ -607,7 +607,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_L) = riscv_f64ToI64 (rm_3b, rs1_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend(rd_val_L);
RETIRE_SUCCESS
}
Expand All @@ -623,7 +623,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_LU) = riscv_f64ToUi64 (rm_3b, rs1_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend(rd_val_LU);
RETIRE_SUCCESS
}
Expand All @@ -639,7 +639,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_D) = riscv_i64ToF64 (rm_3b, rs1_val_L);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_D;
RETIRE_SUCCESS
}
Expand All @@ -655,7 +655,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_D) = riscv_ui64ToF64 (rm_3b, rs1_val_LU);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_D(rd) = rd_val_D;
RETIRE_SUCCESS
}
Expand Down Expand Up @@ -862,7 +862,7 @@ function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FEQ_D)) = {
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f64Eq (rs1_val_D, rs2_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}
Expand All @@ -874,7 +874,7 @@ function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FLT_D)) = {
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f64Lt (rs1_val_D, rs2_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}
Expand All @@ -886,7 +886,7 @@ function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FLE_D)) = {
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f64Le (rs1_val_D, rs2_val_D);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}
Expand Down
28 changes: 14 additions & 14 deletions model/riscv_insts_fext.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -526,7 +526,7 @@ function clause execute (F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, op)) = {
FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b),
FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b))
};
write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_32b;
RETIRE_SUCCESS
}
Expand Down Expand Up @@ -590,7 +590,7 @@ function clause execute (F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, op)) = {
FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b),
FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b)
};
write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_32b;
RETIRE_SUCCESS
}
Expand Down Expand Up @@ -670,7 +670,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FSQRT_S)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_S) = riscv_f32Sqrt (rm_3b, rs1_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_S;
RETIRE_SUCCESS
}
Expand All @@ -685,7 +685,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_W_S)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_W) = riscv_f32ToI32 (rm_3b, rs1_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend (rd_val_W);
RETIRE_SUCCESS
}
Expand All @@ -700,7 +700,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_WU_S)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_WU) = riscv_f32ToUi32 (rm_3b, rs1_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend (rd_val_WU);
RETIRE_SUCCESS
}
Expand All @@ -715,7 +715,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_W)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_S) = riscv_i32ToF32 (rm_3b, rs1_val_W);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_S;
RETIRE_SUCCESS
}
Expand All @@ -730,7 +730,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_WU)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_S) = riscv_ui32ToF32 (rm_3b, rs1_val_WU);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_S;
RETIRE_SUCCESS
}
Expand All @@ -746,7 +746,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_L) = riscv_f32ToI64 (rm_3b, rs1_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend(rd_val_L);
RETIRE_SUCCESS
}
Expand All @@ -762,7 +762,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_LU) = riscv_f32ToUi64 (rm_3b, rs1_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = sign_extend(rd_val_LU);
RETIRE_SUCCESS
}
Expand All @@ -778,7 +778,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_S) = riscv_i64ToF32 (rm_3b, rs1_val_L);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_S;
RETIRE_SUCCESS
}
Expand All @@ -794,7 +794,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU)) = {
let rm_3b = encdec_rounding_mode(rm');
let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU);

write_fflags(fflags);
accrue_fflags(fflags);
F_or_X_S(rd) = rd_val_S;
RETIRE_SUCCESS
}
Expand Down Expand Up @@ -986,7 +986,7 @@ function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FEQ_S)) = {
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f32Eq (rs1_val_S, rs2_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}
Expand All @@ -998,7 +998,7 @@ function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FLT_S)) = {
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f32Lt (rs1_val_S, rs2_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}
Expand All @@ -1010,7 +1010,7 @@ function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FLE_S)) = {
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f32Le (rs1_val_S, rs2_val_S);

write_fflags(fflags);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}
Expand Down
Loading

0 comments on commit 2d18a15

Please sign in to comment.