fix base instruction names

model/riscv_insts_base.sail

@@ -34,7 +34,7 @@ function clause execute UTYPE(imm, rd, op) = {
 mapping utype_mnemonic : uop <-> string = {
   $[name "load upper immediate"]
   RISCV_LUI   <-> "lui",
-  $[name "add upper immediate to pc"]
+  $[name "add upper immediate to PC"]
   RISCV_AUIPC <-> "auipc"
 }
 
@@ -352,25 +352,25 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) = {
 }
 
 mapping rtype_mnemonic : rop <-> string = {
-  $[name "addition"]
+  $[name "add"]
   RISCV_ADD  <-> "add",
-  $[name "signed compare"]
+  $[name "set less than"]
   RISCV_SLT  <-> "slt",
-  $[name "unsigned compare"]
+  $[name "set less than (unsigned)"]
   RISCV_SLTU <-> "sltu",
-  $[name "bitwise logical operation"]
+  $[name "AND"]
   RISCV_AND  <-> "and",
-  $[name "bitwise logical operation"]
+  $[name "OR"]
   RISCV_OR   <-> "or",
-  $[name "bitwise logical operation"]
+  $[name "exclusive XOR"]
   RISCV_XOR  <-> "xor",
-  $[name "logical left shift"]
+  $[name "shift left (logical)"]
   RISCV_SLL  <-> "sll",
-  $[name "logical right shift"]
+  $[name "shift right (logical)"]
   RISCV_SRL  <-> "srl",
-  $[name "subtraction"]
+  $[name "subtract"]
   RISCV_SUB  <-> "sub",
-  $[name "arithmetic right shift"]
+  $[name "shift right (arithmetic)"]
   RISCV_SRA  <-> "sra"
 }
 
@@ -589,15 +589,15 @@ function clause execute (RTYPEW(rs2, rs1, rd, op)) = {
 }
 
 mapping rtypew_mnemonic : ropw <-> string = {
-  $[name "addition (RV64)"]
+  $[name "add word (RV64)"]
   RISCV_ADDW <-> "addw",
-  $[name "subtraction (RV64)"]
+  $[name "subtract word (RV64)"]
   RISCV_SUBW <-> "subw",
-  $[name "logical left shift (RV64)"]
+  $[name "shift left (logical) word (RV64)"]
   RISCV_SLLW <-> "sllw",
-  $[name "logical right shift (RV64)"]
+  $[name "shift right (logical) word (RV64)"]
   RISCV_SRLW <-> "srlw",
-  $[name "arithmetic right shift (RV64)"]
+  $[name "shift right (arithmetic) word (RV64)"]
   RISCV_SRAW <-> "sraw"
 }