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Add names for base instructions
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Linda-Njau committed Jul 24, 2024
1 parent a1c94fe commit 6534dd5
Showing 1 changed file with 18 additions and 0 deletions.
18 changes: 18 additions & 0 deletions model/riscv_insts_base.sail
Original file line number Diff line number Diff line change
Expand Up @@ -32,14 +32,17 @@ function clause execute UTYPE(imm, rd, op) = {
}

mapping utype_mnemonic : uop <-> string = {
$[name "load upper immediate"]
RISCV_LUI <-> "lui",
$[name "add upper immediate to PC"]
RISCV_AUIPC <-> "auipc"
}

mapping clause assembly = UTYPE(imm, rd, op)
<-> utype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_20(imm)

/* ****************************************************************** */
$[name "jump and link"]
union clause ast = RISCV_JAL : (bits(21), regidx)

mapping clause encdec = RISCV_JAL(imm_19 @ imm_7_0 @ imm_8 @ imm_18_13 @ imm_12_9 @ 0b0, rd)
Expand Down Expand Up @@ -349,15 +352,25 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) = {
}

mapping rtype_mnemonic : rop <-> string = {
$[name "add"]
RISCV_ADD <-> "add",
$[name "set less than"]
RISCV_SLT <-> "slt",
$[name "set less than (unsigned)"]
RISCV_SLTU <-> "sltu",
$[name "AND"]
RISCV_AND <-> "and",
$[name "OR"]
RISCV_OR <-> "or",
$[name "exclusive XOR"]
RISCV_XOR <-> "xor",
$[name "shift left (logical)"]
RISCV_SLL <-> "sll",
$[name "shift right (logical)"]
RISCV_SRL <-> "srl",
$[name "subtract"]
RISCV_SUB <-> "sub",
$[name "shift right (arithmetic)"]
RISCV_SRA <-> "sra"
}

Expand Down Expand Up @@ -576,10 +589,15 @@ function clause execute (RTYPEW(rs2, rs1, rd, op)) = {
}

mapping rtypew_mnemonic : ropw <-> string = {
$[name "add word (RV64)"]
RISCV_ADDW <-> "addw",
$[name "subtract word (RV64)"]
RISCV_SUBW <-> "subw",
$[name "shift left (logical) word (RV64)"]
RISCV_SLLW <-> "sllw",
$[name "shift right (logical) word (RV64)"]
RISCV_SRLW <-> "srlw",
$[name "shift right (arithmetic) word (RV64)"]
RISCV_SRAW <-> "sraw"
}

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