Fix case for Zbs instruction names

ThinkOpenly · Aug 15, 2024 · 5c3aad8 · 5c3aad8
1 parent 0000e79
commit 5c3aad8
Showing 1 changed file with 8 additions and 8 deletions.
diff --git a/model/riscv_insts_zbs.sail b/model/riscv_insts_zbs.sail
@@ -22,13 +22,13 @@ mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BSETI) if extension("Zbs")
   <-> 0b001010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if extension("Zbs") & (sizeof(xlen) == 64 | shamt[5] == bitzero)
 
 mapping zbs_iop_mnemonic : biop_zbs <-> string = {
-  $[name "Single-Bit Clear (Immediate)"]
+  $[name "single-bit clear (immediate)"]
   RISCV_BCLRI <-> "bclri",
-  $[name "Single-Bit Extract (Immediate)"]
+  $[name "single-bit extract (immediate)"]
   RISCV_BEXTI <-> "bexti",
-  $[name "Single-Bit Invert (Immediate)"]
+  $[name "single-bit invert (immediate)"]
   RISCV_BINVI <-> "binvi",
-  $[name "Single-Bit Set (Immediate)"]
+  $[name "single-bit set (immediate)"]
   RISCV_BSETI <-> "bseti"
 }
 
@@ -66,13 +66,13 @@ mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BSET) if extension("Zbs")
   <-> 0b0010100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if extension("Zbs")
 
 mapping zbs_rtype_mnemonic : brop_zbs <-> string = {
-  $[name "Single-Bit Clear (Register)"]
+  $[name "single-bit clear (register)"]
   RISCV_BCLR    <-> "bclr",
-  $[name "Single-Bit Extract (Register)"]
+  $[name "single-bit extract (register)"]
   RISCV_BEXT    <-> "bext",
-  $[name "Single-Bit Invert (Register)"]
+  $[name "single-bit invert (register)"]
   RISCV_BINV    <-> "binv",
-  $[name "Single-Bit Set (Register)"]
+  $[name "single-bit set (register)"]
   RISCV_BSET    <-> "bset"
 }