sram: fakeram vs. mock SRAM

Signed-off-by: Øyvind Harboe <[email protected]>

openroad.bzl

@@ -1247,6 +1247,8 @@ STAGE_ARGS_USES = {
     "ROUTING_LAYER_ADJUSTMENT": ["place", "grt", "route", "final"],
     "FILL_CELLS": ["route"],
     "TAPCELL_TCL": ["floorplan"],
+    "ADDITIONAL_LEFS": ["synth", "floorplan", "place", "cts", "grt", "route", "final"],
+    "ADDITIONAL_LIBS": ["synth", "floorplan", "place", "cts", "grt", "route", "final"],
 }
 
 def get_stage_args(stage, stage_args, args):

sram/.gitignore

@@ -0,0 +1 @@
+build/

sram/BUILD

@@ -0,0 +1,128 @@
+load("//:openroad.bzl", "orfs_flow")
+
+orfs_flow(
+    name = "sdq_17x64",
+    abstract_stage = "cts",
+    # FIXME does not work
+    #mock_area = 0.1,
+    args = {
+        "SDC_FILE": "$(location //sram:fakeram/constraints-sram.sdc)",
+        "REMOVE_ABC_BUFFERS": "1",
+        "CORE_UTILIZATION": "20",
+        "CORE_MARGIN": "2",
+        "MACRO_PLACE_HALO": "30 30",
+        "PLACE_DENSITY": "0.25",
+    },
+    stage_sources = {
+        "synth": ["//sram:fakeram/constraints-sram.sdc"],
+    },
+    verilog_files = ["//sram:fakeram/sdq_17x64.sv"],
+)
+
+orfs_flow(
+    name = "top",
+    abstract_stage = "cts",
+    macros = ["//sram:sdq_17x64_generate_abstract"],
+    args = {
+        "SDC_FILE": "$(location //sram:fakeram/constraints-sram.sdc)",
+        "REMOVE_ABC_BUFFERS": "1",
+        "DIE_AREA": "0 0 100 100",
+        "CORE_AREA": "2 2 98 98",
+        "RTLMP_FLOW": "True",
+        "CORE_MARGIN": "2",
+        "MACRO_PLACE_HALO": "2 2",
+    },
+    stage_sources = {
+        "synth": ["//sram:fakeram/constraints-sram.sdc"],
+    },
+    verilog_files = ["//sram:fakeram/top.v"],
+)
+
+orfs_flow(
+    name = "top",
+    variant="fakeram",
+    abstract_stage = "cts",
+    args = {
+        "SDC_FILE": "$(location //sram:fakeram/constraints-sram.sdc)",
+        "REMOVE_ABC_BUFFERS": "1",
+        "DIE_AREA": "0 0 30 30",
+        "CORE_AREA": "2 2 28 28",
+        "RTLMP_FLOW": "True",
+        "CORE_MARGIN": "2",
+        "MACRO_PLACE_HALO": "2 2",
+        "ADDITIONAL_LEFS": "$(location //sram:fakeram/sdq_17x64.lef)",
+        "ADDITIONAL_LIBS": "$(location //sram:fakeram/sdq_17x64.lib)",
+    },
+    stage_sources = {
+        "synth": [
+            "//sram:fakeram/constraints-sram.sdc",
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib",
+        ],
+        "floorplan": [
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib"
+        ],
+        "place": [
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib"
+        ],
+        "cts": [
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib"
+        ],
+        "grt": [
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib"
+        ],
+        "route": [
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib"
+        ],
+        "final": [
+            "//sram:fakeram/sdq_17x64.lef",
+            "//sram:fakeram/sdq_17x64.lib"
+        ]
+    },
+    verilog_files = ["//sram:fakeram/top.v"],
+)
+
+orfs_flow(
+    name = "sdq_17x64",
+    variant = "megaboom",
+    abstract_stage = "cts",
+    # FIXME does not work
+    #mock_area = 0.1,
+    args = {
+        "SDC_FILE": "$(location //sram:megaboom/constraints-sram.sdc)",
+        "REMOVE_ABC_BUFFERS": "1",
+        "CORE_UTILIZATION": "20",
+        "CORE_MARGIN": "2",
+        "MACRO_PLACE_HALO": "30 30",
+        "PLACE_DENSITY": "0.25",
+    },
+    stage_sources = {
+        "synth": ["//sram:megaboom/constraints-sram.sdc"],
+    },
+    verilog_files = ["//sram:megaboom/sdq_17x64.sv"],
+)
+
+orfs_flow(
+    name = "top",
+    abstract_stage = "cts",
+    variant = "megaboom",
+    macros = ["//sram:sdq_17x64_megaboom_generate_abstract"],
+    args = {
+        "SDC_FILE": "$(location //sram:megaboom/constraints-top.sdc)",
+        "REMOVE_ABC_BUFFERS": "1",
+        "DIE_AREA": "0 0 100 100",
+        "CORE_AREA": "2 2 98 98",
+        "RTLMP_FLOW": "True",
+        "CORE_MARGIN": "2",
+        "MACRO_PLACE_HALO": "2 2",
+    },
+    stage_sources = {
+        "synth": ["//sram:megaboom/constraints-top.sdc"],
+    },
+    verilog_files = ["//sram:megaboom/top.v"],
+)

sram/fakeram/constraints-sram.sdc

@@ -0,0 +1,9 @@
+set clk_name clk
+set clk_port_name clk
+set clk_period 400
+
+if { [llength [all_registers]] > 0} {
+  source $env(PLATFORM_DIR)/constraints.sdc
+} else {
+  puts "The design is gutted when mocking floorplan"
+}