Merge pull request openhwgroup#1618 from spidugu444/riscv-arch-test-pr

Use riscv-arch-test suite to verify CVA6 core

.gitlab-ci/cva6.yml

@@ -158,6 +158,33 @@ pub_smoke:
     paths:
       - artifacts/reports/*.yml
 
+pub_riscv_arch_test:
+  stage: two
+  extends:
+    - .template_job_short_ci
+  needs:
+    - job: pub_smoke
+      artifacts: false
+  parallel:
+    matrix:
+      - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x]
+  variables:
+    DV_SIMULATORS: "veri-testharness,spike"
+    DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET"
+    DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
+    DASHBOARD_SORT_INDEX: 0
+    DASHBOARD_JOB_CATEGORY: "Test suites"
+  script:
+    - mkdir -p artifacts/reports
+    - python3 .gitlab-ci/scripts/report_fail.py
+    - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
+    - source cva6/regress/dv-riscv-arch-test.sh
+    - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log
+  artifacts:
+    when: always
+    paths:
+      - "artifacts/reports/*.yml"
+
 pub_hwconfig:
   stage: two
   extends:

cva6/regress/install-riscv-isa-sim.sh

@@ -11,14 +11,19 @@ if ! [ -n "$RISCV_ISA_SIM" ]; then
   RISCV_ISA_SIM="https://github.com/riscv-software-src/riscv-isa-sim.git"
   RISCV_ISA_SIM_BRANCH="master"
   RISCV_ISA_SIM_HASH="b9fc8e4e9087a6064dfcc627efabbe3fd4bdc309"
+  RISCV_ISA_SIM_PATCH="../../../cva6/regress/riscv-isa-sim.patch"
 fi
 echo $RISCV_ISA_SIM
 echo $RISCV_ISA_SIM_BRANCH
 echo $RISCV_ISA_SIM_HASH
+echo $RISCV_ISA_SIM_PATCH
 
 if ! [ -d cva6/tests/riscv-isa-sim ]; then
   git clone $RISCV_ISA_SIM -b $RISCV_ISA_SIM_BRANCH cva6/tests/riscv-isa-sim
   cd cva6/tests/riscv-isa-sim; git checkout $RISCV_ISA_SIM_HASH;
+  if [ -f "$RISCV_ISA_SIM_PATCH" ]; then
+    git apply $RISCV_ISA_SIM_PATCH
+  fi
   cd -
 fi
 

cva6/regress/riscv-isa-sim.patch

@@ -0,0 +1,15 @@
+diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h
+index e968e43a..7628af51 100644
+--- a/arch_test_target/spike/model_test.h
++++ b/arch_test_target/spike/model_test.h
+@@ -23,6 +23,7 @@
+   li x1, 1;                                                                   \
+   write_tohost:                                                               \
+     sw x1, tohost, t1;                                                        \
++  ecall
+   self_loop:  j self_loop;
+
+ #define RVMODEL_BOOT
+-- 
+2.39.0
+

cva6/regress/smoke-tests.sh

@@ -18,6 +18,8 @@ source ./cva6/regress/install-cva6.sh
 source ./cva6/regress/install-riscv-dv.sh
 source ./cva6/regress/install-riscv-compliance.sh
 source ./cva6/regress/install-riscv-tests.sh
+source ./cva6/regress/install-riscv-isa-sim.sh
+source ./cva6/regress/install-riscv-arch-test.sh
 
 if ! [ -n "$DV_SIMULATORS" ]; then
   DV_SIMULATORS=vcs-testharness,spike
@@ -27,13 +29,15 @@ cd cva6/sim/
 python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
 python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
 python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
+python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS  --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld
 python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
 python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\
   --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld"
 make -C ../../core-v-cores/cva6 clean
 make clean_all
 python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
 python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
+python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS  --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld
 make -C ../../core-v-cores/cva6 clean
 make clean_all