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mannual updating of strong odin results update
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@amin1377
amin1377 committed Aug 28, 2024
1 parent 6ba8eb7 commit fe82c32
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6 changes: 3 additions & 3 deletions ...tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 5.41 vpr 210.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 215372 1 4 28 32 2 10 9 4 4 16 clb auto 51.6 MiB 0.14 20 27 15 8 4 193.4 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000583141 0.000535113 0.00311475 0.00261673 8 12 5 72000 72000 5593.62 349.601 2.10 0.0862302 0.0767113 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0109455 0.00960207
timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 7.10 vpr 394.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 403912 1 4 28 32 2 10 9 4 4 16 clb auto 51.6 MiB 0.14 20 27 15 8 4 193.6 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000585834 0.000538181 0.00313704 0.0026163 8 12 5 72000 72000 5593.62 349.601 2.10 0.0854666 0.0759832 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0110022 0.00964644
timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 5.33 vpr 210.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 215036 1 4 28 32 2 10 9 4 4 16 clb auto 51.7 MiB 0.14 20 27 15 8 4 193.7 MiB 0.03 0.00 2.44626 0 0 2.44626 0.50 0.000588315 0.000539577 0.00308844 0.0026033 8 12 5 72000 72000 5593.62 349.601 2.09 0.0840539 0.0747826 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0100088 0.0087372
timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 5.41 vpr 210.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64611 1 4 28 32 2 10 9 4 4 16 clb auto 51.6 MiB 0.14 20 27 15 8 4 193.4 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000583141 0.000535113 0.00311475 0.00261673 8 12 5 72000 72000 5593.62 349.601 2.10 0.0862302 0.0767113 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0109455 0.00960207
timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 7.10 vpr 394.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 80782 1 4 28 32 2 10 9 4 4 16 clb auto 51.6 MiB 0.14 20 27 15 8 4 193.6 MiB 0.03 0.00 2.44626 0 0 2.44626 0.51 0.000585834 0.000538181 0.00313704 0.0026163 8 12 5 72000 72000 5593.62 349.601 2.10 0.0854666 0.0759832 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0110022 0.00964644
timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 5.33 vpr 210.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64510 1 4 28 32 2 10 9 4 4 16 clb auto 51.7 MiB 0.14 20 27 15 8 4 193.7 MiB 0.03 0.00 2.44626 0 0 2.44626 0.50 0.000588315 0.000539577 0.00308844 0.0026033 8 12 5 72000 72000 5593.62 349.601 2.09 0.0840539 0.0747826 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0100088 0.0087372
2 changes: 1 addition & 1 deletion ...ession_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 4.81 vpr 207.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 212752 2 2 22 24 2 4 6 4 4 16 clb auto 51.5 MiB 0.10 4 15 2 10 3 192.8 MiB 0.02 0.00 1.297 0 0 1.297 0.49 0.000472548 0.000433891 0.00258794 0.00211333 4 6 2 72000 36000 2827.54 176.721 1.75 0.0226752 0.0196524 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.02 0.16 -1 -1 0.01 0.00604643 0.0051332
timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 4.81 vpr 207.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63825 2 2 22 24 2 4 6 4 4 16 clb auto 51.5 MiB 0.10 4 15 2 10 3 192.8 MiB 0.02 0.00 1.297 0 0 1.297 0.49 0.000472548 0.000433891 0.00258794 0.00211333 4 6 2 72000 36000 2827.54 176.721 1.75 0.0226752 0.0196524 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.02 0.16 -1 -1 0.01 0.00604643 0.0051332
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