Merge pull request verilog-to-routing#2646 from verilog-to-routing/Yo…

…sys42 Yosys42
SymbiFlow · Aug 23, 2024 · 8f62ad3 · 8f62ad3
2 parents 33a82f1 + 78352e7
commit 8f62ad3
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diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml
@@ -62,9 +62,9 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""}
+          # - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=OFF",                                     extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

diff --git a/parmys/regression_test/benchmark/suite/koios_weekly_suite/task_list.conf b/parmys/regression_test/benchmark/suite/koios_weekly_suite/task_list.conf
@@ -2,5 +2,5 @@ regression_test/benchmark/task/koios/koios_large
 regression_test/benchmark/task/koios/koios_large_no_hb
 regression_test/benchmark/task/koios/koios_proxy
 regression_test/benchmark/task/koios/koios_proxy_no_hb
-regression_test/benchmark/task/koios/koios_sv
-regression_test/benchmark/task/koios/koios_sv_no_hb
+#regression_test/benchmark/task/koios/koios_sv
+#regression_test/benchmark/task/koios/koios_sv_no_hb
diff --git a/parmys/regression_test/benchmark/task/freecores/synthesis_result.json b/parmys/regression_test/benchmark/task/freecores/synthesis_result.json
@@ -479,20 +479,20 @@
         "Multiplier": 1,
         "Memory": 8,
         "generic logic size": 4,
-        "Longest Path": 269,
+        "Longest Path": 274,
         "Average Path": 3,
-        "Estimated LUTs": 4797,
+        "Estimated LUTs": 4777,
         "Total Node": 1957,
-        "Wires": 5595,
-        "Wire Bits": 10315,
+        "Wires": 5591,
+        "Wire Bits": 10025,
         "Public Wires": 240,
         "Public Wire Bits": 240,
-        "Total Cells": 8221,
-        "MUX": 2180,
+        "Total Cells": 8185,
+        "MUX": 2164,
         "XOR": 40,
-        "OR": 2850,
-        "AND": 1455,
-        "NOT": 639,
+        "OR": 2836,
+        "AND": 1451,
+        "NOT": 637,
         "DFFs": [
             "$_DFF_P_ 645"
         ],
@@ -533,8 +533,8 @@
         "Average Path": 3,
         "Estimated LUTs": 41888,
         "Total Node": 5344,
-        "Wires": 9772,
-        "Wire Bits": 102222,
+        "Wires": 9777,
+        "Wire Bits": 102242,
         "Public Wires": 391,
         "Public Wire Bits": 391,
         "Total Cells": 31999,
@@ -585,8 +585,8 @@
         "Average Path": 3,
         "Estimated LUTs": 42386,
         "Total Node": 5593,
-        "Wires": 10802,
-        "Wire Bits": 103242,
+        "Wires": 10796,
+        "Wire Bits": 103210,
         "Public Wires": 648,
         "Public Wire Bits": 648,
         "Total Cells": 32995,
@@ -840,16 +840,16 @@
         "Average Path": 4,
         "Estimated LUTs": 4564,
         "Total Node": 2961,
-        "Wires": 6943,
-        "Wire Bits": 11526,
+        "Wires": 6934,
+        "Wire Bits": 11506,
         "Public Wires": 501,
         "Public Wire Bits": 501,
-        "Total Cells": 8995,
+        "Total Cells": 8955,
         "MUX": 2605,
         "XOR": 311,
-        "OR": 1858,
-        "AND": 1687,
-        "NOT": 711,
+        "OR": 1861,
+        "AND": 1683,
+        "NOT": 672,
         "DFFs": [
             "$_DFF_P_ 1312"
         ],
@@ -861,9 +861,6 @@
         "test_name": "freecores/mips_16/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "warnings": [
-            "mips_16.v:0 System task `$display' outside initial block is unsupported.",
-            "mips_16.v:0 System task `$display' outside initial block is unsupported.",
-            "mips_16.v:0 System task `$display' outside initial block is unsupported.",
             "Replacing memory \\reg_array with list of registers. See ../vtr_flow/benchmarks//freecores/mips_16.v:791",
             "Ignoring module EX_stage because it contains processes (run 'proc' command first).",
             "Ignoring module data_mem because it contains processes (run 'proc' command first).",