Update NoC link bandwidth in the architecture files used for MLP benc…

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SymbiFlow · Sep 7, 2024 · 5118c97 · 5118c97
1 parent c7b9ce0
commit 5118c97
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/...c_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml b/...c_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml
@@ -48449,7 +48449,7 @@
     </switchblock>
   </switchblocklist>
   <!-- The NoC routers were added to the FPGA device in the fixed layout section-->
-  <noc link_bandwidth="1e6" router_latency="1e-9" link_latency="1e-9" noc_router_tile_name="noc_router_adapter">
+  <noc link_bandwidth="1.28e11" router_latency="1e-9" link_latency="1e-9" noc_router_tile_name="noc_router_adapter">
 	  <mesh startx="0" starty="0" endx="340" endy="270" size="4"/>
   </noc>
 </architecture>