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Merge pull request verilog-to-routing#2441 from stef9998/patch-1
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vaughnbetz authored Apr 29, 2024
2 parents c9fcf98 + 3729f70 commit 03fce75
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2 changes: 1 addition & 1 deletion doc/src/vpr/basic_flow.rst
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Expand Up @@ -4,7 +4,7 @@ Basic flow
The Place and Route process in VPR consists of several steps:

- Packing (combinines primitives into complex blocks)
- Placment (places complex blocks within the FPGA grid)
- Placement (places complex blocks within the FPGA grid)
- Routing (determines interconnections between blocks)
- Analysis (analyzes the implementation)

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