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Fix SMP compile-time error when disabling supervisor option #397

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merged 1 commit into from
Mar 10, 2024
Merged

Fix SMP compile-time error when disabling supervisor option #397

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5 changes: 5 additions & 0 deletions src/main/scala/vexriscv/VexRiscv.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,11 @@ case class VexRiscvConfig(){
case None => false
}

def withSupervisor = find(classOf[CsrPlugin]) match {
case Some(x) => x.config.supervisorGen
case None => false
}

def FLEN = if(withRvd) 64 else if(withRvf) 32 else 0

//Default Stageables
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4 changes: 3 additions & 1 deletion src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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Expand Up @@ -206,7 +206,9 @@ class VexRiscvSmpClusterWithPeripherals(p : VexRiscvSmpClusterParameter) extends
plic.priorityWidth.load(2)
plic.mapping.load(PlicMapping.sifive)
plic.addTarget(core.cpu.externalInterrupt)
plic.addTarget(core.cpu.externalSupervisorInterrupt)
if(core.cpu.config.withSupervisor) {
plic.addTarget(core.cpu.externalSupervisorInterrupt)
}
List(clint.logic, core.cpu.logic).produce {
for (plugin <- core.cpu.config.plugins) plugin match {
case plugin: CsrPlugin if plugin.utime != null => plugin.utime := clint.logic.io.time
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