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package vexriscv.demo | ||
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import spinal.core._ | ||
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} | ||
import vexriscv.plugin._ | ||
import vexriscv.{VexRiscv, VexRiscvConfig, plugin} | ||
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||
/** | ||
* Both iBusTc and dBusTc assume | ||
* - 1 cycle read latency | ||
* - read_data stay on the port until the next access | ||
* - writes should only occure when dBusTc_enable && dBusTc_write_enable | ||
* - address is in byte, don't care about the 2 LSB | ||
*/ | ||
object GenFullWithTcm extends App{ | ||
def config = VexRiscvConfig( | ||
plugins = List( | ||
new IBusCachedPlugin( | ||
prediction = DYNAMIC, | ||
config = InstructionCacheConfig( | ||
cacheSize = 4096, | ||
bytePerLine =32, | ||
wayCount = 1, | ||
addressWidth = 32, | ||
cpuDataWidth = 32, | ||
memDataWidth = 32, | ||
catchIllegalAccess = true, | ||
catchAccessFault = true, | ||
asyncTagMemory = false, | ||
twoCycleRam = true, | ||
twoCycleCache = true | ||
), | ||
memoryTranslatorPortConfig = MmuPortConfig( | ||
portTlbSize = 4 | ||
) | ||
).newTightlyCoupledPort( | ||
TightlyCoupledPortParameter("iBusTc", a => a(31 downto 28) === 0x2) | ||
), | ||
new DBusCachedPlugin( | ||
config = new DataCacheConfig( | ||
cacheSize = 4096, | ||
bytePerLine = 32, | ||
wayCount = 1, | ||
addressWidth = 32, | ||
cpuDataWidth = 32, | ||
memDataWidth = 32, | ||
catchAccessError = true, | ||
catchIllegal = true, | ||
catchUnaligned = true | ||
), | ||
memoryTranslatorPortConfig = MmuPortConfig( | ||
portTlbSize = 6 | ||
) | ||
).newTightlyCoupledPort( | ||
TightlyCoupledDataPortParameter("dBusTc", a => a(31 downto 28) === 0x3) | ||
), | ||
new MmuPlugin( | ||
virtualRange = _(31 downto 28) === 0xC, | ||
ioRange = _(31 downto 28) === 0xF | ||
), | ||
new DecoderSimplePlugin( | ||
catchIllegalInstruction = true | ||
), | ||
new RegFilePlugin( | ||
regFileReadyKind = plugin.SYNC, | ||
zeroBoot = false | ||
), | ||
new IntAluPlugin, | ||
new SrcPlugin( | ||
separatedAddSub = false, | ||
executeInsertion = true | ||
), | ||
new FullBarrelShifterPlugin, | ||
new HazardSimplePlugin( | ||
bypassExecute = true, | ||
bypassMemory = true, | ||
bypassWriteBack = true, | ||
bypassWriteBackBuffer = true, | ||
pessimisticUseSrc = false, | ||
pessimisticWriteRegFile = false, | ||
pessimisticAddressMatch = false | ||
), | ||
new MulPlugin, | ||
new DivPlugin, | ||
new CsrPlugin(CsrPluginConfig.small(0x80000020l)), | ||
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), | ||
new BranchPlugin( | ||
earlyBranch = false, | ||
catchAddressMisaligned = true | ||
), | ||
new YamlPlugin("cpu0.yaml") | ||
) | ||
) | ||
|
||
def cpu() = new VexRiscv( | ||
config | ||
) | ||
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SpinalVerilog(cpu()) | ||
} |
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