fix my bad conflict resolution

SpinalHDL · Mar 22, 2024 · 7b520aa · 7b520aa
1 parent 02ada2a
commit 7b520aa
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -87,7 +87,7 @@ case class CsrPluginConfig(
                             exportPrivilege     : Boolean = false,
                             var withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation
                             var debugTriggers       : Int     = 2,
-                            var debugTriggersLsu : Boolean = false
+                            var debugTriggersLsu : Boolean = false,
                             // these options only have effect, when no CounterService is present in Pipeline
                             utimeAccess         : CsrAccess = CsrAccess.NONE,
                             mcycleAccess        : CsrAccess = CsrAccess.NONE,