Add feature so that mmcfg_base reads address for all buses available

Signed-off-by: Sae86 <[email protected]>

chipsec/hal/mmio.py

@@ -412,9 +412,14 @@ def list_MMIO_BARs(self) -> None:
     ##################################################################################
     # Access to Memory Mapped PCIe Configuration Space
     ##################################################################################
-
-    def get_MMCFG_base_address(self) -> Tuple[int, int]:
-        (bar_base, bar_size) = self.get_MMIO_BAR_base_address('MMCFG')
+    def get_MMCFG_base_addresses(self) -> List[Tuple[int, int]]:
+        mmcfg_base_address_list = []
+        for bus in self.cs.Cfg.CONFIG_PCI['MemMap_VTd']['bus']:
+            mmcfg_base_address_list.append(self.get_MMCFG_base_address(bus))
+        return mmcfg_base_address_list
+
+    def get_MMCFG_base_address(self, bus: Optional[int] = None) -> Tuple[int, int]:
+        (bar_base, bar_size) = self.get_MMIO_BAR_base_address('MMCFG', bus)
         if self.cs.register.has_field("PCI0.0.0_PCIEXBAR", "LENGTH") and not self.cs.is_server():
             len = self.cs.register.read_field("PCI0.0.0_PCIEXBAR", "LENGTH")
             if len == PCI_PCIEXBAR_REG_LENGTH_256MB:

chipsec/utilcmd/mmcfg_base_cmd.py

@@ -46,10 +46,12 @@ def parse_arguments(self) -> None:
 
     def run(self) -> None:
         _mmio = mmio.MMIO(self.cs)
-        pciexbar, pciexbar_sz = _mmio.get_MMCFG_base_address()
-        self.logger.log(f'[CHIPSEC] Memory Mapped Config Base: 0x{pciexbar:016X}')
-        self.logger.log(f'[CHIPSEC] Memory Mapped Config Size: 0x{pciexbar_sz:016X}')
-        self.logger.log('')
+        pciexbarlist = _mmio.get_MMCFG_base_addresses()
+        for pciexbar in pciexbarlist:
+            self.logger.log(f'[CHIPSEC] Memory Mapped Config Base: 0x{pciexbar[0]:016X}')
+            self.logger.log(f'[CHIPSEC] Memory Mapped Config Size: 0x{pciexbar[1]:016X}')
+            self.logger.log('')
+
 
 
 commands = {'mmcfg_base': MMCfgBaseCommand}