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Fix address of UART_3 in Renoir
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Signed-off-by: Nathaniel Mitchell <[email protected]>
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npmitche committed Oct 13, 2023
1 parent 2358adf commit cfcac7f
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion chipsec/cfg/1022/renoir.xml
Original file line number Diff line number Diff line change
Expand Up @@ -147,7 +147,7 @@ The following registers are defined in the reference PPR but have not been inclu
<range name="DMA_2" access="mmio" address="0xFEDCD000" size="0x0FFF" />
<range name="DMA_3" access="mmio" address="0xFEDCE000" size="0x0FFF" />
<range name="UART_2" access="mmio" address="0xFEDCF000" size="0x0FFF" />
<range name="UART_3" access="mmio" address="00FEDD0000" size="0x4FFF" />
<range name="UART_3" access="mmio" address="0xFEDD0000" size="0x4FFF" />
<!-- See below for a more detailed breakdown of EMMC Control Space -->
<range name="EMMC_Control" access="mmio" address="0xFEDD5000" size="0x0FFF" />

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