WIP: Add feature to automatically generate url for return codes

Signed-off-by: Sae86 <[email protected]>

chipsec/library/module_ids.json

@@ -0,0 +1 @@
+{"chipsec.modules.bios_kbrd_buffer": 108312180, "chipsec.modules.common.bios_smi": 204199644, "chipsec.modules.common.bios_ts": 145697866, "chipsec.modules.common.bios_wp": 193154049, "chipsec.modules.common.cet": 255569653, "chipsec.modules.common.debugenabled": 119500305, "chipsec.modules.common.ia32cfg": 237600201, "chipsec.modules.common.memconfig": 153156562, "chipsec.modules.common.memlock": 163539152, "chipsec.modules.common.me_mfg_mode": 159788087, "chipsec.modules.common.remap": 108967309, "chipsec.modules.common.rtclock": 8021026, "chipsec.modules.common.sgx_check": 82627414, "chipsec.modules.common.smm": 136211688, "chipsec.modules.common.smm_code_chk": 52475936, "chipsec.modules.common.smm_dma": 142904285, "chipsec.modules.common.smrr": 24264423, "chipsec.modules.common.spd_wd": 118214919, "chipsec.modules.common.spi_access": 72318534, "chipsec.modules.common.spi_desc": 71072845, "chipsec.modules.common.spi_fdopss": 50654249, "chipsec.modules.common.spi_lock": 224775005, "chipsec.modules.common.cpu.cpu_info": 83457459, "chipsec.modules.common.cpu.ia_untrusted": 252569854, "chipsec.modules.common.cpu.spectre_v2": 39646508, "chipsec.modules.common.secureboot.variables": 210110053, "chipsec.modules.common.uefi.access_uefispec": 76692542, "chipsec.modules.common.uefi.s3bootscript": 146016928, "chipsec.modules.tools.wsmt": 239904442, "chipsec.modules.tools.cpu.sinkhole": 8256205, "chipsec.modules.tools.secureboot.te": 24205520, "chipsec.modules.tools.smm.rogue_mmio_bar": 114949610, "chipsec.modules.tools.smm.smm_ptr": 124753037, "chipsec.modules.tools.uefi.reputation": 32972749, "chipsec.modules.tools.uefi.s3script_modify": 254255606, "chipsec.modules.tools.uefi.scan_blocked": 242632605, "chipsec.modules.tools.uefi.scan_image": 90983053, "chipsec.modules.tools.uefi.uefivar_fuzz": 24791044, "chipsec.modules.tools.vmm.common": 176284027, "chipsec.modules.tools.vmm.cpuid_fuzz": 112801485, "chipsec.modules.tools.vmm.ept_finder": 121258294, "chipsec.modules.tools.vmm.hypercallfuzz": 3736407, "chipsec.modules.tools.vmm.iofuzz": 184623991, "chipsec.modules.tools.vmm.msr_fuzz": 248526150, "chipsec.modules.tools.vmm.pcie_fuzz": 144508011, "chipsec.modules.tools.vmm.pcie_overlap_fuzz": 98012164, "chipsec.modules.tools.vmm.venom": 149188924, "chipsec.modules.tools.vmm.hv.define": 213691401, "chipsec.modules.tools.vmm.hv.hypercall": 68298546, "chipsec.modules.tools.vmm.hv.hypercallfuzz": 122154567, "chipsec.modules.tools.vmm.hv.synth_dev": 145490087, "chipsec.modules.tools.vmm.hv.synth_kbd": 251258484, "chipsec.modules.tools.vmm.hv.vmbus": 18544249, "chipsec.modules.tools.vmm.hv.vmbusfuzz": 258248042, "chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase": 233706947, "chipsec.modules.tools.vmm.xen.define": 31261358, "chipsec.modules.tools.vmm.xen.hypercall": 218038015, "chipsec.modules.tools.vmm.xen.hypercallfuzz": 184734627, "chipsec.modules.tools.vmm.xen.xsa188": 143117306}

chipsec/library/url.py

@@ -0,0 +1,51 @@
+# CHIPSEC: Platform Security Assessment Framework
+# Copyright (c) 2024, Intel Corporation
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# as published by the Free Software Foundation; Version 2.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+#
+# Contact information:
+# [email protected]
+#
+
+"""
+Common include file for modules
+
+"""
+
+import os
+import json
+
+
+class url: 
+    def __init__(self, cs):
+        self.url_info = self.get_url_info()
+        self.base_url = self.get_base_url()
+        self.replace_find = self.url_info.get('replace_find', [''])
+        self.replace_with = self.url_info.get('replace_with', '')
+        self.ends_with = self.url_info.get('ends_with', '')
+
+    def get_url_info(self):
+        with open(os.path.join(os.getcwd(), 'url_format.json'), 'r') as url_file:
+            return  json.loads(url_file.read())
+
+    def get_base_url(self):
+        if 'base_url' not in self.url_info:
+            raise Exception("Missing Base URL in url file")
+        return self.url_info['base_url']
+
+    def get_module_url(self, module_name: str) -> str:
+        for item in self.replace_find:
+            module_name.replace(item, self.replace_with)
+        module_url = f'{self.base_url}{module_name}{self.ends_with}'
+        return module_url

chipsec/library/url_format.json

@@ -0,0 +1 @@
+{"base_url": "https://chipsec.github.io/modules/", "replace_find": [("")], "replace_with": "", "endswith": ".html"}

chipsec/module.py

@@ -22,8 +22,9 @@
 import re
 import os
 import traceback
-import pickle
-import chipsec.library.logger
+import json
+from chipsec.library.logger import logger
+from chipsec.library.url import url
 from chipsec.library.returncode import ModuleResult, generate_hash_id
 
 _importlib = True
@@ -37,11 +38,12 @@
 
 class Module:
     def __init__(self, name):
-        self.logger = chipsec.library.logger.logger()
+        self.logger = logger()
         self.name = name
         self.module = None
         self.mod_obj = None
         self.module_ids = self.get_module_ids_dictionary()
+        self.url = url()
 
     def __lt__(self, other):
         return self.name < other.name
@@ -77,15 +79,15 @@ def do_import(self):
         return loaded
 
     def get_module_ids_dictionary(self):
-        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.pkl'), 'rb') as module_ids_file:
-            module_ids = pickle.load(module_ids_file)
+        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.json'), 'r') as module_ids_file:
+            module_ids = json.loads(module_ids_file.read())
         return module_ids
 
     def update_module_ids_file(self):
-        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.pkl'), 'wb') as module_ids_file:
-            pickle.dump(self.module_ids, module_ids_file)
+        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.json'), 'w') as module_ids_file:
+            module_ids_file.write(json.dumps(self.module_ids))
 
-    def get_module_id(self, module_name):
+    def get_module_id(self, module_name):  
         if module_name in self.module_ids:
             module_id = self.module_ids[module_name]
         else:
@@ -105,6 +107,7 @@ def run(self, module_argv):
 
         if isinstance(self.mod_obj, chipsec.module_common.BaseModule):
             self.mod_obj.result.id = self.get_module_id(self.name)
+            self.mod_obj.result.url = self.url.get_module_url(self.name)
             if self.mod_obj.is_supported():
                 result = self.mod_obj.run(module_argv)
             else:

chipsec/modules/common/bios_kbrd_buffer.py

@@ -46,7 +46,6 @@
 class bios_kbrd_buffer(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_kbrd_buffer.html'
 
     def is_supported(self) -> bool:
         return True

chipsec/modules/common/bios_smi.py

@@ -54,7 +54,6 @@ class bios_smi(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_smi.html'
 
     def is_supported(self) -> bool:
         if not self.cs.control.is_defined('SmmBiosWriteProtection') or \

chipsec/modules/common/bios_ts.py

@@ -47,7 +47,6 @@
 class bios_ts(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_ts.html'
 
     def is_supported(self) -> bool:
         if self.cs.control.is_defined('BiosInterfaceLockDown'):

chipsec/modules/common/bios_wp.py

@@ -71,7 +71,6 @@ class bios_wp(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self.spi = SPI(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_wp.html'
 
     def is_supported(self) -> bool:
         ble_exists = self.cs.control.is_defined('BiosLockEnable')

chipsec/modules/common/cet.py

@@ -42,7 +42,6 @@
 class cet(BaseModule):
     def __init__(self):
         super(cet, self).__init__()
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.cet.html'
         self.cpuid_7_0__ecx_val = None
 
     def is_supported(self):

chipsec/modules/common/debugenabled.py

@@ -52,7 +52,6 @@ class debugenabled(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.debugenabled.html'
         self.is_enable_set = False
         self.is_debug_set = False
         self.is_lock_set = True

chipsec/modules/common/me_mfg_mode.py

@@ -101,7 +101,6 @@ class me_mfg_mode(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.me_mfg_mode.html'
 
     def is_supported(self) -> bool:
         if self.cs.device.is_enabled("MEI1"):

chipsec/modules/common/memconfig.py

@@ -46,7 +46,6 @@ class memconfig(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.memconfig.html'
         self.memmap_registers = {
             "PCI0.0.0_GGC": 'GGCLOCK',
             "PCI0.0.0_PAVPC": 'PAVPLCK',

chipsec/modules/common/memlock.py

@@ -53,7 +53,6 @@ class memlock(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.memlock.html'
         self.is_read_error = False
 
     def is_supported(self) -> bool:

chipsec/modules/common/remap.py

@@ -60,7 +60,6 @@ class remap(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.remap.html'
 
     def is_supported(self) -> bool:
         if self.cs.is_core():

chipsec/modules/common/rtclock.py

@@ -52,7 +52,6 @@ class rtclock(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self.cmos = CMOS(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.rtclock.html'
         self.user_request = False
         self.test_offset = 0x38
         self.test_value = 0xAA

chipsec/modules/common/sgx_check.py

@@ -72,7 +72,6 @@
 class sgx_check(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.sgx_check.html'
         self.helper = self.cs.helper
         self.res = ModuleResult.PASSED
 

chipsec/modules/common/smm.py

@@ -48,7 +48,6 @@ class smm(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smm.html'
 
     def is_supported(self) -> bool:
         if self.cs.is_core() and self.cs.register.is_defined('PCI0.0.0_SMRAMC'):

chipsec/modules/common/smm_code_chk.py

@@ -54,7 +54,6 @@ class smm_code_chk(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smm_code_chk.html'
 
     def is_supported(self) -> bool:
         if not self.cs.register.is_defined('MSR_SMM_FEATURE_CONTROL'):

chipsec/modules/common/smm_dma.py

@@ -68,7 +68,6 @@ class smm_dma(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smm_dma.html'
 
     def is_supported(self) -> bool:
         if self.cs.is_atom():

chipsec/modules/common/smrr.py

@@ -62,7 +62,6 @@ class smrr(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smrr.html'
 
     def is_supported(self) -> bool:
         mtrr_exist = self.cs.register.is_defined('MTRRCAP')

chipsec/modules/common/spd_wd.py

@@ -61,7 +61,6 @@ class spd_wd(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spd_wd.html'
 
     def is_supported(self) -> bool:
         if self.cs.device.is_enabled('SMBUS'):

chipsec/modules/common/spi_access.py

@@ -58,7 +58,6 @@ class spi_access(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self.spi = SPI(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_access.html'
 
     def is_supported(self) -> bool:
         if self.cs.register.has_field('HSFS', 'FDV') and self.cs.register.has_field('FRAP', 'BRWA'):

chipsec/modules/common/spi_desc.py

@@ -51,7 +51,6 @@ class spi_desc(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_desc.html'
 
     def is_supported(self) -> bool:
         if self.cs.register.has_all_fields('FRAP', ['BRRA', 'BRWA']):

chipsec/modules/common/spi_fdopss.py

@@ -44,7 +44,6 @@ class spi_fdopss(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_fdopss.html'
 
     def is_supported(self) -> bool:
         if not self.cs.register.has_field('HSFS', 'FDOPSS'):

chipsec/modules/common/spi_lock.py

@@ -54,7 +54,6 @@ class spi_lock(BaseModule):
 
     def __init__(self):
         super(spi_lock, self).__init__()
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_lock.html'
 
     def is_supported(self) -> bool:
         if self.cs.control.is_defined('FlashLockDown'):

chipsec/modules/common/uefi/access_uefispec.py

@@ -56,7 +56,6 @@ class access_uefispec(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self._uefi = UEFI(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.uefi.access_uefispec.html'
 
         nv = EFI_VARIABLE_NON_VOLATILE
         bs = EFI_VARIABLE_BOOTSERVICE_ACCESS

chipsec/modules/tools/cpu/sinkhole.py

@@ -56,7 +56,6 @@ class sinkhole(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.cpu.sinkhole.html'
 
     def is_supported(self):
         if not (self.cs.os_helper.is_windows() or self.cs.os_helper.is_linux()):

chipsec/modules/tools/generate_test_id.py

@@ -39,7 +39,6 @@
 class generate_test_id(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.generate_test_id.html'
 
     def usage(self):
         self.logger.log(__doc__.replace('`', ''))

chipsec/modules/tools/secureboot/te.py

@@ -494,7 +494,6 @@ class te(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.secureboot.te.html'
 
     def is_supported(self):
         #win8 = self.cs.helper.is_win8_or_greater()

chipsec/modules/tools/smm/rogue_mmio_bar.py

@@ -71,7 +71,6 @@ class rogue_mmio_bar(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self._interrupts = Interrupts(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.rogue_mmio_bar.html'
 
         # SMI code to be written to I/O port 0xB2
         self.smic_start = 0x00

chipsec/modules/tools/smm/smm_ptr.py

@@ -189,7 +189,6 @@ def __init__(self):
         self.test_ptr_in_buffer = False
         self.fill_byte = _MEM_FILL_VALUE
         self.fill_size = _MEM_FILL_SIZE
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.smm_ptr.html'
 
     def is_supported(self):
         return True

chipsec/modules/tools/uefi/reputation.py

@@ -56,7 +56,6 @@ class reputation(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.uefi.reputation.html'
         self.uefi = UEFI(self.cs)
         self.image = None
         self.vt_threshold = 10

chipsec/modules/tools/uefi/scan_blocked.py

@@ -69,7 +69,7 @@ class scan_blocked(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.uefi.scan_blocked.html'
+
         self.uefi = UEFI(self.cs)
         self.cfg_name = 'blockedlist.json'
         self.image = None

chipsec/modules/tools/uefi/uefivar_fuzz.py

@@ -76,7 +76,6 @@ class uefivar_fuzz(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.uefi.uefivar_fuzz.html'
         self._uefi = UEFI(self.cs)
 
     def is_supported(self):

chipsec/modules/tools/vmm/cpuid_fuzz.py

@@ -87,7 +87,6 @@
 class cpuid_fuzz (BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.cpuid_fuzz.html'
 
     def fuzz_CPUID(self, eax_start, random_order = False):
         eax_range = _NO_EAX_TO_FUZZ

chipsec/modules/tools/vmm/hv/hypercallfuzz.py

@@ -48,7 +48,6 @@
 class HypercallFuzz(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html'
 
     def usage(self):
         print('  Usage:')

chipsec/modules/tools/vmm/hv/synth_dev.py

@@ -97,7 +97,6 @@ def print_statistics(self):
 class synth_dev(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_dev.html'
 
     def usage(self):
         print('  Usage:')

chipsec/modules/tools/vmm/hv/synth_kbd.py

@@ -74,7 +74,6 @@ def ringbuffer_read(self):
 class synth_kbd(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_kbd.html'
 
     def usage(self):
         print('  Usage:')

chipsec/modules/tools/vmm/hv/vmbusfuzz.py

@@ -65,7 +65,6 @@ def __init__(self):
         self.fuzzing = False
         self.fuzzing_rules = {}
         self.current_message = 0
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.html'
 
     ##
     # hv_post_msg - Fuzzing a message to be sent