WIP: Add feature to automatically generate url for return codes

Signed-off-by: Sae86 <[email protected]>
Sae86 · May 15, 2024 · b21bcff · b21bcff
1 parent 9c5e35d
commit b21bcff
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Showing 48 changed files with 20 additions and 50 deletions.
diff --git a/chipsec/library/module_ids.json b/chipsec/library/module_ids.json
@@ -0,0 +1 @@
+{"chipsec.modules.bios_kbrd_buffer": 108312180, "chipsec.modules.common.bios_smi": 204199644, "chipsec.modules.common.bios_ts": 145697866, "chipsec.modules.common.bios_wp": 193154049, "chipsec.modules.common.cet": 255569653, "chipsec.modules.common.debugenabled": 119500305, "chipsec.modules.common.ia32cfg": 237600201, "chipsec.modules.common.memconfig": 153156562, "chipsec.modules.common.memlock": 163539152, "chipsec.modules.common.me_mfg_mode": 159788087, "chipsec.modules.common.remap": 108967309, "chipsec.modules.common.rtclock": 8021026, "chipsec.modules.common.sgx_check": 82627414, "chipsec.modules.common.smm": 136211688, "chipsec.modules.common.smm_code_chk": 52475936, "chipsec.modules.common.smm_dma": 142904285, "chipsec.modules.common.smrr": 24264423, "chipsec.modules.common.spd_wd": 118214919, "chipsec.modules.common.spi_access": 72318534, "chipsec.modules.common.spi_desc": 71072845, "chipsec.modules.common.spi_fdopss": 50654249, "chipsec.modules.common.spi_lock": 224775005, "chipsec.modules.common.cpu.cpu_info": 83457459, "chipsec.modules.common.cpu.ia_untrusted": 252569854, "chipsec.modules.common.cpu.spectre_v2": 39646508, "chipsec.modules.common.secureboot.variables": 210110053, "chipsec.modules.common.uefi.access_uefispec": 76692542, "chipsec.modules.common.uefi.s3bootscript": 146016928, "chipsec.modules.tools.wsmt": 239904442, "chipsec.modules.tools.cpu.sinkhole": 8256205, "chipsec.modules.tools.secureboot.te": 24205520, "chipsec.modules.tools.smm.rogue_mmio_bar": 114949610, "chipsec.modules.tools.smm.smm_ptr": 124753037, "chipsec.modules.tools.uefi.reputation": 32972749, "chipsec.modules.tools.uefi.s3script_modify": 254255606, "chipsec.modules.tools.uefi.scan_blocked": 242632605, "chipsec.modules.tools.uefi.scan_image": 90983053, "chipsec.modules.tools.uefi.uefivar_fuzz": 24791044, "chipsec.modules.tools.vmm.common": 176284027, "chipsec.modules.tools.vmm.cpuid_fuzz": 112801485, "chipsec.modules.tools.vmm.ept_finder": 121258294, "chipsec.modules.tools.vmm.hypercallfuzz": 3736407, "chipsec.modules.tools.vmm.iofuzz": 184623991, "chipsec.modules.tools.vmm.msr_fuzz": 248526150, "chipsec.modules.tools.vmm.pcie_fuzz": 144508011, "chipsec.modules.tools.vmm.pcie_overlap_fuzz": 98012164, "chipsec.modules.tools.vmm.venom": 149188924, "chipsec.modules.tools.vmm.hv.define": 213691401, "chipsec.modules.tools.vmm.hv.hypercall": 68298546, "chipsec.modules.tools.vmm.hv.hypercallfuzz": 122154567, "chipsec.modules.tools.vmm.hv.synth_dev": 145490087, "chipsec.modules.tools.vmm.hv.synth_kbd": 251258484, "chipsec.modules.tools.vmm.hv.vmbus": 18544249, "chipsec.modules.tools.vmm.hv.vmbusfuzz": 258248042, "chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase": 233706947, "chipsec.modules.tools.vmm.xen.define": 31261358, "chipsec.modules.tools.vmm.xen.hypercall": 218038015, "chipsec.modules.tools.vmm.xen.hypercallfuzz": 184734627, "chipsec.modules.tools.vmm.xen.xsa188": 143117306}
diff --git a/chipsec/library/module_ids.pkl b/chipsec/library/module_ids.pkl
diff --git a/chipsec/library/url_format.json b/chipsec/library/url_format.json
@@ -0,0 +1 @@
+{"base_url": "https://chipsec.github.io/modules/", "replace": "", "with": "", "endswith": ".html"}
diff --git a/chipsec/module.py b/chipsec/module.py
@@ -22,7 +22,7 @@
 import re
 import os
 import traceback
-import pickle
+import json
 import chipsec.library.logger
 from chipsec.library.returncode import ModuleResult, generate_hash_id
 
@@ -77,13 +77,13 @@ def do_import(self):
         return loaded
 
     def get_module_ids_dictionary(self):
-        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.pkl'), 'rb') as module_ids_file:
-            module_ids = pickle.load(module_ids_file)
+        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.json'), 'r') as module_ids_file:
+            module_ids = json.loads(module_ids_file.read())
         return module_ids
 
     def update_module_ids_file(self):
-        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.pkl'), 'wb') as module_ids_file:
-            pickle.dump(self.module_ids, module_ids_file)
+        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'module_ids.json'), 'w') as module_ids_file:
+            module_ids_file.write(json.dumps(self.module_ids))
 
     def get_module_id(self, module_name):
         if module_name in self.module_ids:
@@ -94,6 +94,17 @@ def get_module_id(self, module_name):
             self.update_module_ids_file() 
         return module_id
 
+    def get_url_info(self):
+        with open(os.path.join(os.getcwd(), 'chipsec', 'library', 'url_format.json'), 'r') as url_file:
+            url_info = json.loads(url_file.read())
+        return url_info
+
+    def get_module_url(self, module_name: str):
+        url_info = self.get_url_info()
+        module_name.replace(url_info['replace'], url_info['with'])
+        module_url = f'{url_info["base_url"]}{module_name}{url_info["endswith"]}'
+        return module_url
+
     def run(self, module_argv):
         self.get_module_object()
 
@@ -105,6 +116,7 @@ def run(self, module_argv):
 
         if isinstance(self.mod_obj, chipsec.module_common.BaseModule):
             self.mod_obj.result.id = self.get_module_id(self.name)
+            self.mod_obj.result.url = self.get_module_url(self.name)
             if self.mod_obj.is_supported():
                 result = self.mod_obj.run(module_argv)
             else:

diff --git a/chipsec/modules/common/bios_kbrd_buffer.py b/chipsec/modules/common/bios_kbrd_buffer.py
@@ -46,7 +46,6 @@
 class bios_kbrd_buffer(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_kbrd_buffer.html'
 
     def is_supported(self) -> bool:
         return True

diff --git a/chipsec/modules/common/bios_smi.py b/chipsec/modules/common/bios_smi.py
@@ -54,7 +54,6 @@ class bios_smi(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_smi.html'
 
     def is_supported(self) -> bool:
         if not self.cs.control.is_defined('SmmBiosWriteProtection') or \

diff --git a/chipsec/modules/common/bios_ts.py b/chipsec/modules/common/bios_ts.py
@@ -47,7 +47,6 @@
 class bios_ts(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_ts.html'
 
     def is_supported(self) -> bool:
         if self.cs.control.is_defined('BiosInterfaceLockDown'):

diff --git a/chipsec/modules/common/bios_wp.py b/chipsec/modules/common/bios_wp.py
@@ -71,7 +71,6 @@ class bios_wp(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self.spi = SPI(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.bios_wp.html'
 
     def is_supported(self) -> bool:
         ble_exists = self.cs.control.is_defined('BiosLockEnable')

diff --git a/chipsec/modules/common/cet.py b/chipsec/modules/common/cet.py
@@ -42,7 +42,6 @@
 class cet(BaseModule):
     def __init__(self):
         super(cet, self).__init__()
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.cet.html'
         self.cpuid_7_0__ecx_val = None
 
     def is_supported(self):

diff --git a/chipsec/modules/common/debugenabled.py b/chipsec/modules/common/debugenabled.py
@@ -52,7 +52,6 @@ class debugenabled(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.debugenabled.html'
         self.is_enable_set = False
         self.is_debug_set = False
         self.is_lock_set = True

diff --git a/chipsec/modules/common/me_mfg_mode.py b/chipsec/modules/common/me_mfg_mode.py
@@ -101,7 +101,6 @@ class me_mfg_mode(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.me_mfg_mode.html'
 
     def is_supported(self) -> bool:
         if self.cs.device.is_enabled("MEI1"):

diff --git a/chipsec/modules/common/memconfig.py b/chipsec/modules/common/memconfig.py
@@ -46,7 +46,6 @@ class memconfig(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.memconfig.html'
         self.memmap_registers = {
             "PCI0.0.0_GGC": 'GGCLOCK',
             "PCI0.0.0_PAVPC": 'PAVPLCK',

diff --git a/chipsec/modules/common/memlock.py b/chipsec/modules/common/memlock.py
@@ -53,7 +53,6 @@ class memlock(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.memlock.html'
         self.is_read_error = False
 
     def is_supported(self) -> bool:

diff --git a/chipsec/modules/common/remap.py b/chipsec/modules/common/remap.py
@@ -60,7 +60,6 @@ class remap(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.remap.html'
 
     def is_supported(self) -> bool:
         if self.cs.is_core():

diff --git a/chipsec/modules/common/rtclock.py b/chipsec/modules/common/rtclock.py
@@ -52,7 +52,6 @@ class rtclock(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self.cmos = CMOS(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.rtclock.html'
         self.user_request = False
         self.test_offset = 0x38
         self.test_value = 0xAA

diff --git a/chipsec/modules/common/sgx_check.py b/chipsec/modules/common/sgx_check.py
@@ -72,7 +72,6 @@
 class sgx_check(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.sgx_check.html'
         self.helper = self.cs.helper
         self.res = ModuleResult.PASSED
 

diff --git a/chipsec/modules/common/smm.py b/chipsec/modules/common/smm.py
@@ -48,7 +48,6 @@ class smm(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smm.html'
 
     def is_supported(self) -> bool:
         if self.cs.is_core() and self.cs.register.is_defined('PCI0.0.0_SMRAMC'):

diff --git a/chipsec/modules/common/smm_code_chk.py b/chipsec/modules/common/smm_code_chk.py
@@ -54,7 +54,6 @@ class smm_code_chk(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smm_code_chk.html'
 
     def is_supported(self) -> bool:
         if not self.cs.register.is_defined('MSR_SMM_FEATURE_CONTROL'):

diff --git a/chipsec/modules/common/smm_dma.py b/chipsec/modules/common/smm_dma.py
@@ -68,7 +68,6 @@ class smm_dma(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smm_dma.html'
 
     def is_supported(self) -> bool:
         if self.cs.is_atom():

diff --git a/chipsec/modules/common/smrr.py b/chipsec/modules/common/smrr.py
@@ -62,7 +62,6 @@ class smrr(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.smrr.html'
 
     def is_supported(self) -> bool:
         mtrr_exist = self.cs.register.is_defined('MTRRCAP')

diff --git a/chipsec/modules/common/spd_wd.py b/chipsec/modules/common/spd_wd.py
@@ -61,7 +61,6 @@ class spd_wd(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spd_wd.html'
 
     def is_supported(self) -> bool:
         if self.cs.device.is_enabled('SMBUS'):

diff --git a/chipsec/modules/common/spi_access.py b/chipsec/modules/common/spi_access.py
@@ -58,7 +58,6 @@ class spi_access(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self.spi = SPI(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_access.html'
 
     def is_supported(self) -> bool:
         if self.cs.register.has_field('HSFS', 'FDV') and self.cs.register.has_field('FRAP', 'BRWA'):

diff --git a/chipsec/modules/common/spi_desc.py b/chipsec/modules/common/spi_desc.py
@@ -51,7 +51,6 @@ class spi_desc(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_desc.html'
 
     def is_supported(self) -> bool:
         if self.cs.register.has_all_fields('FRAP', ['BRRA', 'BRWA']):

diff --git a/chipsec/modules/common/spi_fdopss.py b/chipsec/modules/common/spi_fdopss.py
@@ -44,7 +44,6 @@ class spi_fdopss(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_fdopss.html'
 
     def is_supported(self) -> bool:
         if not self.cs.register.has_field('HSFS', 'FDOPSS'):

diff --git a/chipsec/modules/common/spi_lock.py b/chipsec/modules/common/spi_lock.py
@@ -54,7 +54,6 @@ class spi_lock(BaseModule):
 
     def __init__(self):
         super(spi_lock, self).__init__()
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.spi_lock.html'
 
     def is_supported(self) -> bool:
         if self.cs.control.is_defined('FlashLockDown'):

diff --git a/chipsec/modules/common/uefi/access_uefispec.py b/chipsec/modules/common/uefi/access_uefispec.py
@@ -56,7 +56,6 @@ class access_uefispec(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self._uefi = UEFI(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.common.uefi.access_uefispec.html'
 
         nv = EFI_VARIABLE_NON_VOLATILE
         bs = EFI_VARIABLE_BOOTSERVICE_ACCESS

diff --git a/chipsec/modules/tools/cpu/sinkhole.py b/chipsec/modules/tools/cpu/sinkhole.py
@@ -56,7 +56,6 @@ class sinkhole(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.cpu.sinkhole.html'
 
     def is_supported(self):
         if not (self.cs.os_helper.is_windows() or self.cs.os_helper.is_linux()):

diff --git a/chipsec/modules/tools/generate_test_id.py b/chipsec/modules/tools/generate_test_id.py
@@ -39,7 +39,6 @@
 class generate_test_id(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.generate_test_id.html'
 
     def usage(self):
         self.logger.log(__doc__.replace('`', ''))

diff --git a/chipsec/modules/tools/secureboot/te.py b/chipsec/modules/tools/secureboot/te.py
@@ -494,7 +494,6 @@ class te(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.secureboot.te.html'
 
     def is_supported(self):
         #win8 = self.cs.helper.is_win8_or_greater()

diff --git a/chipsec/modules/tools/smm/rogue_mmio_bar.py b/chipsec/modules/tools/smm/rogue_mmio_bar.py
@@ -71,7 +71,6 @@ class rogue_mmio_bar(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
         self._interrupts = Interrupts(self.cs)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.rogue_mmio_bar.html'
 
         # SMI code to be written to I/O port 0xB2
         self.smic_start = 0x00

diff --git a/chipsec/modules/tools/smm/smm_ptr.py b/chipsec/modules/tools/smm/smm_ptr.py
@@ -189,7 +189,6 @@ def __init__(self):
         self.test_ptr_in_buffer = False
         self.fill_byte = _MEM_FILL_VALUE
         self.fill_size = _MEM_FILL_SIZE
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.smm_ptr.html'
 
     def is_supported(self):
         return True

diff --git a/chipsec/modules/tools/uefi/reputation.py b/chipsec/modules/tools/uefi/reputation.py
@@ -56,7 +56,6 @@ class reputation(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.uefi.reputation.html'
         self.uefi = UEFI(self.cs)
         self.image = None
         self.vt_threshold = 10

diff --git a/chipsec/modules/tools/uefi/scan_blocked.py b/chipsec/modules/tools/uefi/scan_blocked.py
@@ -69,7 +69,7 @@ class scan_blocked(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.uefi.scan_blocked.html'
+
         self.uefi = UEFI(self.cs)
         self.cfg_name = 'blockedlist.json'
         self.image = None

diff --git a/chipsec/modules/tools/uefi/uefivar_fuzz.py b/chipsec/modules/tools/uefi/uefivar_fuzz.py
@@ -76,7 +76,6 @@ class uefivar_fuzz(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.uefi.uefivar_fuzz.html'
         self._uefi = UEFI(self.cs)
 
     def is_supported(self):

diff --git a/chipsec/modules/tools/vmm/cpuid_fuzz.py b/chipsec/modules/tools/vmm/cpuid_fuzz.py
@@ -87,7 +87,6 @@
 class cpuid_fuzz (BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.cpuid_fuzz.html'
 
     def fuzz_CPUID(self, eax_start, random_order = False):
         eax_range = _NO_EAX_TO_FUZZ

diff --git a/chipsec/modules/tools/vmm/hv/hypercallfuzz.py b/chipsec/modules/tools/vmm/hv/hypercallfuzz.py
@@ -48,7 +48,6 @@
 class HypercallFuzz(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html'
 
     def usage(self):
         print('  Usage:')

diff --git a/chipsec/modules/tools/vmm/hv/synth_dev.py b/chipsec/modules/tools/vmm/hv/synth_dev.py
@@ -97,7 +97,6 @@ def print_statistics(self):
 class synth_dev(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_dev.html'
 
     def usage(self):
         print('  Usage:')

diff --git a/chipsec/modules/tools/vmm/hv/synth_kbd.py b/chipsec/modules/tools/vmm/hv/synth_kbd.py
@@ -74,7 +74,6 @@ def ringbuffer_read(self):
 class synth_kbd(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_kbd.html'
 
     def usage(self):
         print('  Usage:')

diff --git a/chipsec/modules/tools/vmm/hv/vmbusfuzz.py b/chipsec/modules/tools/vmm/hv/vmbusfuzz.py
@@ -65,7 +65,6 @@ def __init__(self):
         self.fuzzing = False
         self.fuzzing_rules = {}
         self.current_message = 0
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.html'
 
     ##
     # hv_post_msg - Fuzzing a message to be sent

diff --git a/chipsec/modules/tools/vmm/hypercallfuzz.py b/chipsec/modules/tools/vmm/hypercallfuzz.py
@@ -82,9 +82,7 @@ class hypercallfuzz(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html'
         self.vmm = VMM(self.cs)
-
         self.random_order = True
         self.gprs = GPRS
         self.vector_reg = None

diff --git a/chipsec/modules/tools/vmm/iofuzz.py b/chipsec/modules/tools/vmm/iofuzz.py
@@ -80,7 +80,6 @@
 class iofuzz(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.iofuzz.html'
 
     def fuzz_ports(self, iterations, write_count, random_order=False):
 

diff --git a/chipsec/modules/tools/vmm/msr_fuzz.py b/chipsec/modules/tools/vmm/msr_fuzz.py
@@ -81,7 +81,6 @@
 class msr_fuzz (BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.msr_fuzz.html'
 
     def fuzz_MSRs(self, msr_addr_start, random_order=False):
         msr_addr_range = 0x10000

diff --git a/chipsec/modules/tools/vmm/pcie_fuzz.py b/chipsec/modules/tools/vmm/pcie_fuzz.py
@@ -79,7 +79,6 @@
 class pcie_fuzz(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_fuzz.html'
 
     def fuzz_io_bar(self, bar, size=0x100):
         port_off = 0

diff --git a/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py b/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py
@@ -68,7 +68,6 @@
 class pcie_overlap_fuzz(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.html'
 
     def overlap_mmio_range(self, bus1, dev1, fun1, is64bit1, off1, bus2, dev2, fun2, is64bit2, off2, direction):
         base_lo1 = self.cs.pci.read_dword(bus1, dev1, fun1, off1)

diff --git a/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py b/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py
@@ -50,7 +50,6 @@
 class vbox_crash_apicbase(BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.html'
 
     def run(self, module_argv):
         self.logger.start_test('Host OS Crash due to IA32_APIC_BASE (Oracle VirtualBox CVE-2015-0377)')

diff --git a/chipsec/modules/tools/vmm/venom.py b/chipsec/modules/tools/vmm/venom.py
@@ -62,7 +62,6 @@
 class venom (BaseModule):
     def __init__(self):
         BaseModule.__init__(self)
-        self.result.url = 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.venom.html'
 
     def venom_impl(self):
         self.cs.io.write_port_byte(FDC_PORT_DATA_FIFO, FD_CMD)