• Verilog Practice Dir updated till 2nd Oct 2024

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• Combinational Circuits:

  • Gates
  • halfadder
  • fulladder
  • concatination
  • multiplexors
  • buffer

• Sequential Circuits:

  • Counters
  • assignment
  • d-flipflop
  • register-file

• Sequential-Combination Circuits

  • finite state machines

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• Single Cycle Dev Dir updated till 16th Oct 2024

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• DRAM [4x72] : -> Dram consists of address of 4 depth and bit size of 72 bits.

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• extensions:

  • Verilog-HDL/SystemVerilog/Bluespec SystemVerilog v1.15
  • Makefile Tools v0.10.26.

src directory contains design files .v ext. tb directory contains test bentch files, that run on gtkwave simmulation file marked with .vcd ext. temp contains output and vcd files.