Programming interface #3532
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Programming interface #3532
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randyh62
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Jul 26, 2024
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| The programming interface document will focus on the HIP runtime API. The runtime API provides C and C++ functions for event, stream, device and memory managements, etc. The HIP runtime on AMD platform uses the Common Language Runtimes (CLR), while on NVIDIA platform HIP runtime is only a thin layer over the CUDA runtime. | ||
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| - **CLR** contains source codes for AMD's compute languages runtimes: ``HIP`` and ``OpenCL™``. CLR includes the implementation of ``HIP`` language on the AMD platform `hipamd <https://github.com/ROCm/clr/tree/develop/hipamd>`_ and the Radeon Open Compute Common Language Runtime (rocclr). rocclr is a virtual device interface, that HIP runtime interact with different backends such as ROCr on Linux or PAL on Windows. (CLR also include the implementation of `OpenCL <https://github.com/ROCm/clr/tree/develop/opencl>`_, while it's interact with ROCr and PAL) |
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CLR contains source codes for AMD's common languages runtimes:
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MKKnorr
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docs/understand/hip_runtime_api.rst
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| Read-only storage visible to all threads in a given grid. It is a limited | ||
| segment of global with queryable size. |
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I think this should highlight the differences to global memory, i.e. (possibly) different caching, and performance recommendations.
Also I'm not sure if it's really a segment of global memory (which is a logical partition), but rather part of device memory (as in physically located there)
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| Read-only storage visible to all threads in a given grid. It is a limited | |
| segment of global with queryable size. | |
| Read-only storage visible to all threadson a given device. It is a limited | |
| segment backed by device memory with queryable size. It needs to be set by the host before kernel execution. | |
| Constant memory provides the best performance benefit when all threads within a warp access the same address. |
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Maybe here given grid was better. Updated. Let's discuss offline.
docs/understand/hip_runtime_api.rst
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| Unified Memory is a single memory address space accessible from any processor | ||
| within a system. This setup simplifies memory management processes and enables | ||
| applications to allocate data that can be read or written by code running on | ||
| either CPUs or GPUs. The Unified memory model is shown in the following figure. |
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There is no figure here :)
Also, should the performance implications be mentioned here?
MKKnorr
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@randyh62 The programming interface currently.