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| .. list-table:: | ||
| :header-rows: 1 | ||
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| * - **Environment variable** | ||
| - **Default value** | ||
| - **Usage** | ||
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| * - | ``AMD_LOG_LEVEL`` | ||
| | Enable HIP log on different Level | ||
| - 0 | ||
| - | 0: Disable log. | ||
| | 1: Enable log on error level | ||
| | 2: Enable log on warning and below levels | ||
| | 0x3: Enable log on information and below levels | ||
| | 0x4: Decode and display AQL packets | ||
| * - | ``AMD_LOG_MASK`` | ||
| | Enable HIP log on different Level | ||
| - 0x7FFFFFFF | ||
| - | 0x1: Log API calls | ||
| | 0x02: Kernel and Copy Commands and Barriers | ||
| | 0x4: Synchronization and waiting for commands to finish | ||
| | 0x8: Enable log on information and below levels | ||
| | 0x20: Queue commands and queue contents | ||
| | 0x40: Signal creation, allocation, pool | ||
| | 0x80: Locks and thread-safety code | ||
| | 0x100: Copy debug | ||
| | 0x200: Detailed copy debug | ||
| | 0x400: Resource allocation, performance-impacting events | ||
| | 0x800: Initialization and shutdown | ||
| | 0x1000: Misc debug, not yet classified | ||
| | 0x2000: Show raw bytes of AQL packet | ||
| | 0x4000: Show code creation debug | ||
| | 0x8000: More detailed command info, including barrier commands | ||
| | 0x10000: Log message location | ||
| | 0xFFFFFFFF: Log always even mask flag is zero | ||
| * - | ``HIP_LAUNCH_BLOCKING`` | ||
| | Used for serialization on kernel execution. | ||
| - 0 | ||
| - | 0: Disable. Kernel executes normally. | ||
| | 1: Enable. Serializes kernel enqueue, behaves the same as AMD_SERIALIZE_KERNEL. | ||
| * - | ``HIP_VISIBLE_DEVICES`` (or ``CUDA_VISIBLE_DEVICES``) | ||
| | Only devices whose index is present in the sequence are visible to HIP | ||
| - | ||
| - 0,1,2: Depending on the number of devices on the system | ||
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| * - | ``GPU_DUMP_CODE_OBJECT`` | ||
| | Dump code object | ||
| - 0 | ||
| - | 0: Disable | ||
| | 1: Enable | ||
| * - | ``AMD_SERIALIZE_KERNEL`` | ||
| | Serialize kernel enqueue | ||
| - 0 | ||
| - | 1: Wait for completion before enqueue | ||
| | 2: Wait for completion after enqueue | ||
| | 3: Both | ||
| * - | ``AMD_SERIALIZE_COPY`` | ||
| | Serialize copies | ||
| - 0 | ||
| - | 1: Wait for completion before enqueue | ||
| | 2: Wait for completion after enqueue | ||
| | 3: Both | ||
| * - | ``HIP_HOST_COHERENT`` | ||
| | Coherent memory in hipHostMalloc | ||
| - 0 | ||
| - | 0: memory is not coherent between host and GPU | ||
| | 1: memory is coherent with host | ||
| * - | ``AMD_DIRECT_DISPATCH`` | ||
| | Enable direct kernel dispatch (Currently for Linux; under development for Windows) | ||
| - 1 | ||
| - | 0: Disable | ||
| | 1: Enable | ||
| * - | ``GPU_MAX_HW_QUEUES`` | ||
| | The maximum number of hardware queues allocated per device | ||
| - 4 | ||
| - The variable controls how many independent hardware queues HIP runtime can create per process, | ||
| per device. If an application allocates more HIP streams than this number, then HIP runtime reuses | ||
| the same hardware queues for the new streams in a round-robin manner. Note that this maximum | ||
| number does not apply to hardware queues that are created for CU-masked HIP streams, or | ||
| cooperative queues for HIP Cooperative Groups (single queue per device). |
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| Original file line number | Diff line number | Diff line change |
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| .. meta:: | ||
| :description: HIP environment variables reference | ||
| :keywords: AMD, HIP, environment variables, environment, reference | ||
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| ************************************************************* | ||
| HIP environment variables | ||
| ************************************************************* | ||
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| In this section the reader can find all the important HIP environment variables. | ||
| The full collection of the environment variables can be found at | ||
| :doc:`ROCm environment variables page<rocm:reference/env-variables>` | ||
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| GPU isolation | ||
| ============= | ||
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| The GPU isolation environment variables in HIP is collected in the next table. | ||
| For details how to use the variables check the :doc:`GPU isolation page <rocm:conceptual/gpu-isolation>` | ||
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| .. list-table:: | ||
| :header-rows: 1 | ||
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| * - **Environment variable** | ||
| - **Example value** | ||
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| * - | ``ROCR_VISIBLE_DEVICES`` | ||
| | A list of device indices or UUIDs that will be exposed to applications. | ||
| - ``0,GPU-DEADBEEFDEADBEEF`` | ||
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| * - | ``GPU_DEVICE_ORDINAL`` | ||
| | Devices indices exposed to OpenCL and HIP applications. | ||
| - ``0,2`` | ||
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| * - | ``HIP_VISIBLE_DEVICES`` or ``CUDA_VISIBLE_DEVICES`` | ||
| | Device indices exposed to HIP applications. | ||
| - ``0,2`` | ||
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| Profiling environment variables | ||
| =============================== | ||
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| The profiling environment variables in HIP is collected in the next table. For | ||
| details how to use the variables check the :doc:`Setting the number of CUs page <rocm:conceptual/settings-cu>` | ||
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| .. list-table:: | ||
| :header-rows: 1 | ||
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| * - **Environment variable** | ||
| - **Example value** | ||
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| * - | ``HSA_CU_MASK`` | ||
| | Sets the mask on a lower level of queue creation in the driver, | ||
| | this mask will also be set for queues being profiled. | ||
| - | ||
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| * - | ``ROC_GLOBAL_CU_MASK`` | ||
| | Sets the mask on queues created by the HIP or the OpenCL runtimes, | ||
| | this mask will also be set for queues being profiled. | ||
| - | ||
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| * - | ``ROCR_VISIBLE_DEVICES`` | ||
| | A list of device indices or UUIDs that will be exposed to applications. | ||
| - ``0,GPU-DEADBEEFDEADBEEF`` | ||
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| Debug environment variables | ||
| =========================== | ||
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| The debuging environment variables in HIP is collected in the next table. For | ||
| details how to use the debug variables check the :ref:`debugging_with_hip` | ||
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| .. include:: ../how-to/debugging_env.rst | ||
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| Memory management related environment variables | ||
| =============================================== | ||
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| The memory management related environment variables in HIP is collected in the | ||
| next table. | ||
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| .. list-table:: | ||
| :widths: 70,15,15 | ||
| :header-rows: 1 | ||
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| * - Environment variable | ||
| - Variable type | ||
| - Default value | ||
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| * - | ``HIP_HIDDEN_FREE_MEM`` | ||
| | Reserve free mem reporting in Mb, 0 = Disable | ||
| - ``uint`` | ||
| - 0 | ||
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| * - | ``HIP_HOST_COHERENT`` | ||
| | Coherent memory in ``hipHostMalloc`` | ||
| - ``uint`` | ||
| - 0 | ||
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| * - | ``HIP_INITIAL_DM_SIZE`` | ||
| | Set initial heap size for device malloc. The default value corresponds to 8 MiB | ||
| - ``size_t`` | ||
| - 8388608 | ||
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| * - | ``HIP_MEM_POOL_SUPPORT`` | ||
| | Enables memory pool support in HIP | ||
| - ``bool`` | ||
| - ``false`` | ||
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| * - | ``HIP_MEM_POOL_USE_VM`` | ||
| | Enables memory pool support in HIP | ||
| - ``bool`` | ||
| - | ``true`` on Windows, | ||
| | ``false`` on other OS | ||
| * - | ``HIP_VMEM_MANAGE_SUPPORT`` | ||
| | Virtual Memory Management Support | ||
| - ``bool`` | ||
| - ``true`` | ||
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| * - | ``GPU_MAX_HEAP_SIZE`` | ||
| | Set maximum size of the GPU heap to % of board memory | ||
| - ``uint`` | ||
| - 100 | ||
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| * - | ``GPU_MAX_REMOTE_MEM_SIZE`` | ||
| | Maximum size , in Ki that allows device memory substitution with system | ||
| - ``uint`` | ||
| - 2 | ||
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| * - | ``GPU_NUM_MEM_DEPENDENCY`` | ||
| | Number of memory objects for dependency tracking | ||
| - ``size_t`` | ||
| - 256 | ||
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| * - | ``GPU_STREAMOPS_CP_WAIT`` | ||
| | Force the stream wait memory operation to wait on CP. | ||
| - ``bool`` | ||
| - ``false`` | ||
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| * - | ``HSA_LOCAL_MEMORY_ENABLE`` | ||
| | Enable HSA device local memory usage | ||
| - ``bool`` | ||
| - ``true`` | ||
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| * - | ``PAL_ALWAYS_RESIDENT`` | ||
| | Force memory resources to become resident at allocation time | ||
| - ``bool`` | ||
| - ``false`` | ||
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| * - | ``PAL_PREPINNED_MEMORY_SIZE`` | ||
| | Size in KBytes of prepinned memory | ||
| - ``size_t`` | ||
| - 64 | ||
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| * - | ``REMOTE_ALLOC`` | ||
| | Use remote memory for the global heap allocation | ||
| - ``bool`` | ||
| - ``false`` |
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