Refactor after rebase

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "suite/auto-sync/vendor/tree-sitter-cpp"]
-	path = suite/auto-sync/vendor/tree-sitter-cpp
-	url = https://github.com/tree-sitter/tree-sitter-cpp.git

CMakeLists.txt

@@ -1,8 +1,6 @@
 # For MSVC_RUNTIME_LIBRARY
 cmake_minimum_required(VERSION 3.15)
 
-add_compile_options(-Wunused-function -Warray-bounds -Wunused-variable -Wparentheses -Wint-in-bool-context)
-
 if(CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR)
     message(FATAL_ERROR "In-tree builds are not supported. Run CMake from a separate directory: cmake -B build")
 endif()

MCInst.c

@@ -299,21 +299,4 @@ void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
 	MI->Opcode = TmpMI->Opcode;
 	assert(MI->size < MAX_MC_OPS);
 	memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
-}
-
-void MCInst_setIsAlias(MCInst *MI, bool Flag) {
-	assert(MI);
-	MI->isAliasInstr = Flag;
-	MI->flat_insn->is_alias = Flag;
-}
-
-/// @brief Copies the relevant members of a temporary MCInst to
-/// the main MCInst. This is used if TryDecode was run on a temporary MCInst.
-/// @param MI The main MCInst
-/// @param TmpMI The temporary MCInst.
-void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
-	MI->size = TmpMI->size;
-	MI->Opcode = TmpMI->Opcode;
-	assert(MI->size < MAX_MC_OPS);
-	memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
-}
+}

MCInstrDesc.h

@@ -34,13 +34,6 @@ typedef enum {
 	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
 } MCOI_OperandConstraint;
 
-// Define a macro to produce each constraint value.
-#define CONSTRAINT_MCOI_TIED_TO(op) \
-  ((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
-
-#define CONSTRAINT_MCOI_EARLY_CLOBBER \
-  (1 << MCOI_EARLY_CLOBBER)
-
 // Define a macro to produce each constraint value.
 #define CONSTRAINT_MCOI_TIED_TO(op) \
   ((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))

arch/AArch64/AArch64AddressingModes.h

@@ -209,7 +209,7 @@ AArch64_AM_getArithExtendType(unsigned Imm)
 ///            101 ==> sxth
 ///            110 ==> sxtw
 ///            111 ==> sxtx
-inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
+static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
 {
 	switch (ET) {
 	default:

arch/AArch64/AArch64BaseInfo.c

@@ -118,8 +118,6 @@
 
 #undef SysReg
 
-#undef SysReg
-
 // return a string representing the number X
 // NOTE: result must be big enough to contain the data
 static void utostr(uint64_t X, bool isNeg, char *result)

arch/AArch64/AArch64BaseInfo.h

@@ -45,9 +45,6 @@
 #define GET_SUBTARGETINFO_ENUM
 #include "AArch64GenSubtargetInfo.inc"
 
-#define GET_SUBTARGETINFO_ENUM
-#include "AArch64GenSubtargetInfo.inc"
-
 #define GET_REGINFO_ENUM
 #define GET_REGINFO_MC_DESC
 #include "AArch64GenRegisterInfo.inc"
@@ -695,10 +692,6 @@ typedef enum ShiftExtSpecifiers {
 
 // CS namespace begin: AArch64SysReg
 
-// CS namespace end: AArch64Layout
-
-// CS namespace begin: AArch64SysReg
-
 typedef struct SysReg {
 	const char *Name;
 	aarch64_sysop_reg SysReg;

arch/AArch64/AArch64GenAsmWriter.inc

@@ -18246,13 +18246,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
     printSVERegOp_d(MI, 2, O);
     return;
     break;
-  case 85:
-    // TBLQ_ZZZ_D, TBL_ZZZZ_D, TBL_ZZZ_D
-    printTypedVectorList_0_d(MI, 1, O);
-    SStream_concat0(O, ", ");
-    printSVERegOp_d(MI, 2, O);
-    return;
-    break;
   case 86:
     // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB...
     printTypedVectorList_16_b(MI, 1, O);
@@ -19138,14 +19131,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
     printVectorIndex_1(MI, 6, O);
     return;
     break;
-  case 38:
-    // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFDOT...
-    printSVERegOp_h(MI, 5, O);
-    break;
-  case 39:
-    // BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG4_4Z2Z_H, BFMAX_VG2_2Z2Z_H, BFMAX_VG4_4Z...
-    printTypedVectorList_0_h(MI, 2, O);
-    break;
   case 40:
     // BFMLA_ZZZI, BFMLS_ZZZI, CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_Z...
     printVectorIndex_1(MI, 4, O);
@@ -19225,10 +19210,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
     SStream_concat0(O, ", mul vl]");
     return;
     break;
-  case 55:
-    // INSERT_MXIPZ_H_B, INSERT_MXIPZ_V_B, SDOT_VG2_M2ZZI_BToS, SDOT_VG2_M2ZZ...
-    printSVERegOp_b(MI, 5, O);
-    break;
   case 56:
     // LD1B_VG2_M2ZPXX, LDNT1B_VG2_M2ZPXX
     printRegWithShiftExtend_0_8_x_0(MI, 3, O);
@@ -19253,30 +19234,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
     SStream_concat1(O, ']');
     return;
     break;
-  case 55:
-    // LD1B_VG2_M2ZPXI, LD1H_VG2_M2ZPXI, LDNT1B_VG2_M2ZPXI, LDNT1H_VG2_M2ZPXI
-    printImmScale_2(MI, 3, O);
-    SStream_concat0(O, ", mul vl]");
-    return;
-    break;
-  case 56:
-    // LD1B_VG2_M2ZPXX, LDNT1B_VG2_M2ZPXX
-    printRegWithShiftExtend_0_8_x_0(MI, 3, O);
-    SStream_concat1(O, ']');
-    return;
-    break;
-  case 57:
-    // LD1H_VG2_M2ZPXX, LDNT1H_VG2_M2ZPXX
-    printRegWithShiftExtend_0_16_x_0(MI, 3, O);
-    SStream_concat1(O, ']');
-    return;
-    break;
-  case 58:
-    // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX...
-    SStream_concat0(O, "/z, [");
-    printOperand(MI, 4, O);
-    SStream_concat0(O, ", ");
-    break;
   case 60:
     // LDG, ST2GPostIndex, ST2GPreIndex, STGPostIndex, STGPreIndex, STZ2GPost...
     printImmScale_16(MI, 3, O);
@@ -19342,12 +19299,6 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
     SStream_concat1(O, ']');
     return;
     break;
-  case 70:
-    // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q
-    printMatrixIndex(MI, 4, O);
-    SStream_concat1(O, ']');
-    return;
-    break;
   case 71:
     // MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZMXI_H_H, MOVA_2ZMXI_H_S, MOVA_2...
     printImmRangeScale_2_1(MI, 3, O);
@@ -33422,6 +33373,9 @@ static void printCustomAliasOperand(
   case 12:
     printImm(MI, OpIdx, OS);
     break;
+  case 13:
+    printSVEPattern(MI, OpIdx, OS);
+    break;
   case 14:
     printImm8OptLsl_int8_t(MI, OpIdx, OS);
     break;
@@ -33438,7 +33392,7 @@ static void printCustomAliasOperand(
     printImm8OptLsl_int32_t(MI, OpIdx, OS);
     break;
   case 19:
-    printImm8OptLsl_int32_t(MI, OpIdx, OS);
+    printInverseCondCode(MI, OpIdx, OS);
     break;
   case 20:
     printSVELogicalImm_int16_t(MI, OpIdx, OS);
@@ -33458,9 +33412,6 @@ static void printCustomAliasOperand(
   case 25:
     printZPRasFPR_64(MI, OpIdx, OS);
     break;
-  case 25:
-    printZPRasFPR_64(MI, OpIdx, OS);
-    break;
   case 26:
     printZPRasFPR_16(MI, OpIdx, OS);
     break;
@@ -33477,16 +33428,13 @@ static void printCustomAliasOperand(
     printMatrixTileVector_0(MI, OpIdx, OS);
     break;
   case 31:
-    printMatrixTileVector<0>(MI, OpIdx, OS);
-    break;
-  case 32:
-    printMatrixTileVector_1(MI, OpIdx, OS);
+    printMatrixIndex(MI, OpIdx, OS);
     break;
   case 32:
     printMatrixTileVector_1(MI, OpIdx, OS);
     break;
-  case 34:
-    printTypedVectorList_0_d(MI, OpIdx, OS);
+  case 33:
+    printFPImmOperand(MI, OpIdx, OS);
     break;
   case 34:
     printTypedVectorList_0_d(MI, OpIdx, OS);
@@ -33500,8 +33448,8 @@ static void printCustomAliasOperand(
   case 37:
     printBTIHintOp(MI, OpIdx, OS);
     break;
-  case 39:
-    printTypedVectorList_0_b(MI, OpIdx, OS);
+  case 38:
+    printPSBHintOp(MI, OpIdx, OS);
     break;
   case 39:
     printTypedVectorList_0_b(MI, OpIdx, OS);
@@ -33561,17 +33509,14 @@ static void printCustomAliasOperand(
     printMatrix_64(MI, OpIdx, OS);
     break;
   case 58:
-    printMatrix<64>(MI, OpIdx, OS);
+    printImmHex(MI, OpIdx, OS);
     break;
   case 59:
     printPrefetchOp_1(MI, OpIdx, OS);
     break;
   case 60:
     printPrefetchOp_0(MI, OpIdx, OS);
     break;
-  case 60:
-    printPrefetchOp(MI, OpIdx, OS);
-    break;
   case 61:
     printGPR64as32(MI, OpIdx, OS);
     break;